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'Fracturing' FPGAs: the right methods will ensure PCB and FPGA timing and connectivity are in sync. (Design Techniques).

Field-programmable gate arrays (FPGAs) have proven a valuable technology, offering performance, time-to-market and cost advantages over application specific integrated circuits (ASICs). Today many circuit boards contain at least one FPGA. But does the placement process compromise those benefits? And what are the issues of FPGA-on-board integration, including independent FPGA and PCB design processes, high pin count packages, changing pin assignments, high-speed I/O and other factors?

Routing interconnect delays on the FPGA significantly affect the overall circuit performance and led to the development of physical FPGA synthesis tools. Routing interconnect delays on high-density PCBs significantly affect overall board performance and can compromise FPGA performance too. As such, a new approach is needed to solve this huge FPGA-on-board problem, and to handle easily the complexities of placing large, fast-edged FPGA devices on the PCB. These complexities can be broken down into connectivity and timing closure issues, and addressed with process integration for ease-of-use.

Often FPGAs--and, increasingly, PCBs--are designed by separate teams of designers. These design teams are quite different from each other and each has its own processes and requirements. FPGAs are primarily designed and described in a hardware description language (HDL), feeding downstream logic and physical synthesis steps. In contrast, PCB designs are still largely schematically based with no equivalent synthesis steps.

With the huge FPGA devices and packages now available (for example, the 1517-ball flip-chip BGA), it is imperative that basic connectivity data, pin data and status (locked or unlocked, and so on), can be passed easily between the diverse PCB and FPGA design processes. This information needs to be passed alongside key implementation constraints including part, speed-grade, I/O slew-rate and other buffering type constraints. Also, design changes made during the FPGA design process with the appropriate design checks need to be passed from the FPGA back to the PCB designers.

PCB librarians typically create component symbols to be used within the PCB schematic. These symbols are considered static and owned by the librarian. The large number of pins offered by the FPGA coupled with its programmability creates the need for a "custom" FPGA symbol. In many cases, the PCB logic designer chooses to create a custom symbol, so the pin names reflect the user-defined FPGA signal names for easy schematic wiring. Without these custom symbols, the PCB logic designer would be faced with connecting a signal "ABC" to "Bank_2_IOPAD_54"; a painful process when parts have in excess of 1000 pins. A custom symbol permits the PCB logic designer to wire pin "ABC" to signal "ABC." The custom symbol provides for a more expedient and less error-prone process. In addition, the custom symbol should be automatically generated based on the FPGA pin assignment file.

For larger FPGA devices (for example, the Altera Stratix and APEX-II families and the Xilinx Virtex-II and Virtex-II Pro families), schematically representing the symbol for PCB design and documentation is no longer feasible or even physically possible without violating corporate drafting standards. Bear in mind that for even the largest drawing sheet available, the maximum symbol size that can be successfully supported is around 1100 symbol pins.

The PCB designer must be able to "fracture" the FPGA symbol along functional or physical lines. Custom-symbol generation should be augmented with a fracturing capability that enables the user to create a set of custom symbols for a particular FPGA implementation (FIGURE 1). The FPGA symbol set can then be spread conveniently through the PCB schematic for efficient design creation.

[FIGURE 1 OMITTED]

In addition to the custom schematic symbols required for PCB design and layout, PCB tools need accurate and comprehensive symbol-to-part packaging data, often referred to as symbol-to-pin-mapping information.

For large and complex FPGA devices, this has been a long, tedious and error-prone process, taking designers and librarians days to create and verify the symbol and pin-mapping data before confidently proceeding to PCB layout.

(There is novel software that addresses the FPGA and PCB design process synchronization, fully automates this custom symbol and part creation process. FPGA BoardLink, which integrates with Mentor Graphics' PCB and FPGA design tools, ties the custom FPGA symbol and part-creation process into the overall corporate library environment and extracts and uses corporate library part data when generating custom symbols and custom parts for each FPGA device on the PCB.)

Ideally, the PCB designer needs to extract and include PCB interconnect effects for simulation and timing analysis, and then pass these effects easily to the FPGA designer, who immediately benefits from more accurate "Offset Constraints" for the logical and physical FPGA synthesis steps. The interconnect adds delay due to time-of-flight calculations from delay-per-unit trace length plus additional delay due to loads and topology. These modified offset constraints also need to be passed from the synthesis engine to the FPGA vendor implementation tools. Historically, this has been difficult, and compounded by the lack of a common constraint manager that could be used by both PCB and FPGA designers.

In FIGURE 2, functional simulation and timing analysis show a healthy amount of "Offset In--Before'" or "Setup" timing slack. However, actual simulation of the signal and board topology shows that the effects of the PCB interconnect have significantly reduced the amount of available timing slack. This is because the receiver will only see valid transitions when the signal levels at the receiver cross the switching thresholds. The effects are driver-strength-dependent, topology-dependent and termination-dependent.

[FIGURE 2 OMITTED]

Now the functionally estimated offset constraint has been reduced to the more accurate or actual offset constraint. This new reduced value is then passed to the FPGA design tools.

For timing closure, one option is functional simulation of the FPGA-on-board using FPGA vendor-generated standard delay format (SDF) and HDL outputs. Novel symbolic timing analysis can be used with FPGA vendor-supplied modeling information to estimate and analyze the path used to get data on and off the FPGA. In such cases, board analysis is localized around the FPGA and immediate devices, and a simple critical timing-based model used for the FPGA. Calculated or estimated offsets are used to constrain the analysis-driven PCB router, which then derives the actual offset constraints" for FPGA synthesis. The FPGA is then synthesized and placed and routed using the actual offset constraints. The FPGA timing model is generated and timing analysis can be run on either the localized FPGA area of the PCB or on the complete PCB.

ANDY WATTS is product marketing manager, Mentor Graphics Systems Design Division (mentor.com). He can be reached at andy_watts@mentor.com.
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Author:Watts, Andy
Publication:Printed Circuit Design & Manufacture
Date:May 1, 2003
Words:1079
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