parvus Corp. Unveils its PC/104 PowerPC Microcontroller Delivering Rich I/O Functionality for Embedded Computers.Business Editors/High-Tech Writers Embedded Systems Conference San Francisco 2003 Booth #2144 SAN FRANCISCO--(BUSINESS WIRE)--April 23, 2003 PPC/104-555 CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. Board from parvus Corp. Based on Motorola MPC (1) (Mobile PC) A handheld or laptop computer. See handheld computer, laptop computer and Ultra-Mobile PC. (2) (MultiPath Channel) See multipath. 555 parvus Corp. today announced the availability of its PPC/104-555 PC/104 PowerPC module, the first CPU for embedded PC/104 computers to offer the powerful 32-bit Motorola(R) MPC555 chip architecture. The product is priced at $734/each in volume orders of 100+ units. Especially suited for control-intensive applications where timing and control of moving parts are critical, such as in vehicular, robotics, and control automation environments, parvus' PowerPC CPU offers embedded developers a wealth of memory and I/O functionality. This PC/104 form factor board (3.550" x 3.750") is extended temperature rated (-40(degree)C to 85(degree)C) and comes with 488K of onchip Flash, up to 32MB of external Flash, up to 4MB SRAM See static RAM. SRAM - static random-access memory , and 1MB of EEPROM (Electrically Erasable Programmable ROM) A rewritable memory chip that holds its content without power. Although EEPROMs spawned flash memory, EEPROMs are byte addressable at the write level, whereas flash chips must erase a block of bytes before rewriting. memory. The module also features 32 configurable digital I/O channels, two CAN 2.0B modules, two RS-232 serial ports, an alphanumeric LCD port, and a complete timing system. The board's PowerPC architecture provides an ideal foundation for RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. (Reduced Instruction Set Computer (processor) Reduced Instruction Set Computer - (RISC) A processor whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a Complex Instruction Set Computer). ) computing applications, allowing quick execution of instructions, faster time to market and lower production costs. FEATURES & SPECIFICATIONS -- 16-bit PC/104 Bus -- 32-Bit MPC555 Motorola Processor -- Uses PowerPC 603 Code Set -- 32 Digital I/O Points -- Up to 32MB Flash, 4MB SRAM, 1MB EEPROM -- 2 CAN 2.0B Ports (for DeviceNET) -- 2 RS-232 Serial Ports -- 32 12-bit A/D A/D See advance-decline line (A/D). and 8 16-bit D/A D/A See: Documents Against Acceptance Channels -- 64-bit Timebase, Real-Time Clock Alphanumeric LCD Port -- Debug and JTAG Interface -- 5 or 3.3 VDC Power Input -- Compatible w/ Green Hill, Metrowerks, etc. -- Dimensions: 3.550" x 3.750" -- Operating Temperature: -40(degree)C to 85(degree)C About parvus parvus Corp. is a leading manufacturer and systems integrator of modular embedded computer boards, enclosures, displays and systems based on the PC/104 circuit board standard. Its rugged, embedded PC products offer commercial-off-the-shelf (COTS) solutions ideal for avionics, military, medical, industrial, and transportation OEMs. For more information, visit www.parvus.com or call 801/483-1533. |
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