interHDL introduces three new HDL products: ViPact for gate-level analysis of design hot spots, ViCover for code coverage analysis, VHDLlint for code cleanup.

SANTA CLARA, Calif.--(BUSINESS WIRE)--April 2, 1997--International Verilog Conference (IVC) and VHDL International User Forum (VIUF) -- interHDL, a supplier of Electronic Design Automation (EDA) tools for hardware description language (HDL) designers, today announced that it is introducing three new HDL tools.

"We are the HDL technology company," said Eli Sternheim, interHDL president and founder. "These new tools fit with our strategy to support HDL standards and HDL designers worldwide with the tools they need to improve their productivity and the quality of their designs."

ViPact, a power analyzer, and ViCover, a HDL code coverage tool, represent the company's first entries into the design analysis market, which according to the EDA Consortium's Market Statistics Service (MSS) is one of the fastest growing EDA tool segments.

VHDLlint cleans up VHDL code and complements the company's other HDL linter, Verilint, for Verilog HDL cleanup.

About ViPact for Verilog and VHDL

ViPact is a gate-level power analysis tool that determines what components contribute significantly to power consumption in a chip.

Dick Bosenko, interHDL's vice-president of marketing, noted, "ViPact's gate-level power analysis takes minutes, the same analysis done at the transistor-level takes hours. ViPact pinpoints the hot spots in a design. Later, if required, a transistor-level tool, can be used to further analyze just those spots with more accuracy."

ViPact handles designs of up to a million gates. It uses HDL netlists or an EDIF netlist, and a database containing short circuit current information for the ASIC library. This data is used to compute design component power consumption.

Power analysis can be performed before or after synthesis. Inputs are: Verilog or VHDL netlists, EDIF files, Model Technologies' HDL simulators' waveform files and Verilog VCD (Value-Change-Dump) files. ViPact's output is suitable for use with transistor-level tools such as SPICE and EPIC's Powermill.

ViPact was developed for interHDL by a major fabless semiconductor company, where it has been in use for over a year. Along with ViPact, interHDL offers ViLibr, a tool, for characterizing short circuit current data for ASIC libraries, and ViGraph, a graphical user interface (GUI) for ViPact.

About ViCover for Verilog and VHDL

ViCover is a HDL code coverage analyzer. It looks at simulation results to determine whether all the HDL code was analyzed. It outputs a coverage report.

About VHDLlint for VHDL

VHDLlint is a semantics, synthesis and coding-style checker for VHDL. Like Verilint, interHDL's popular Verilog code checker, VHDLlint identifies coding-style errors that may cause problems or may not be identified by simulation and synthesis tools. Using interHDL's linters saves time by eliminating simulation and synthesis runs for code checking.

According to Dick Bosenko's, interHDL, vice president of marketing, added, "Our linters are the defacto standard for HDL code checking. Our customers use our linters to check their code as part of their overall design methodology."

Pricing and Availability

ViPact, ViCover for Verilog, and VHDLlint are available now for UNIX (Sun, HP, DEC Alpha, IBM RS6000, HAL and Linux). Windows and Windows NT versions ship in June. Prices range from $10,000(US) to $30,000(US).

ViCover for VHDL ships in June.

All of interHDL's products support IEEE standards -- 1076 and 1364, as well at EDIF.

interHDL at IVC

interHDL new products, HDL translators and Verilog application tool kits are being demonstrated at IVC/VIUF, April 1 through April 2, at the Santa Clara Convention Center.

About interHDL

interHDL, Inc. was founded in 1992 to develop and sell HDL-related EDA tools. The company sells its design tools directly in the United States and markets its tools internationally through distributors. Customers include: computer, telecommunications and semiconductor companies.

For information about interHDL's tools contact: interHDL Inc., 4984 El Camino Real, Ste. 210, Los Altos, CA 94022-1433, Phone: [phone] or 415/428-4200, Fax: [phone], [e-mail] . Visit interHDL's Web site at http://www.interHDL.com . -0-

Note to Editors: ViPact, ViCover, Verilint and VHDLlint graphics are available as Powerpoint files. -0- Acronyms:

ASIC Application Specific Integrated Circuit EDA Electronic Design Automation EDAC Electronic Design Automation Consortium EDIF Electronic Data Interchange Format HDL Hardware Description Language IVC International Verilog Conference MSS Market Statistics Service VHDL VHSIC (Very High Speed Integrated Circuit) HDL (IEEE 1076) VIUF VHDL International User Forum -0-

interHDL , ViPact, ViCover, Verilint VHDLlint, and the interHDL logo are trademarks of interHDL, Inc.

All other trademarks are properties of their owners.

CONTACT: interHDL

Georgia Marszalek (PR counsel), 415/345-7477

[e-mail]