iRoC Announces New Error Protection for Memories; M-RoCKIT Platform Boosts Error Correction Generation for SoC Designs.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Jan. 16, 2003 iRoC Technologies, a leader in the field of Infrastructure IP, announced today the release of the beta version A pre-shipping release of hardware or software that has gone through alpha test. A beta version of software is supposed to be very close to the final product, but, in practice, it is more a way of getting users to test the software in the first place under real conditions. of M-RoCKIT(TM), a new technology platform for automated generation, interconnection and insertion of advanced error correcting code (ECC (1) (Error-Correcting Code) A type of memory that corrects errors on the fly. See ECC memory. (2) (Elliptic Curve Cryptography) A public key cryptography method that provides fast decryption and digital signature processing. ) for protection against bit flips Switching a bit from 0 to 1 or 1 to 0. Also refers to changing one's mind 180 degrees. See bit flipping. in embedded Inserted into. See embedded system. memories. Today's SoC designers are facing the double challenge of: -- Increased sensitivity of memories to bit flips for new technologies together with an increased amount of Mbits of memories on SoCs -- Increased diversity of memories in SoCs (over 100 memory types). iRoC developed with the M-RoCKIT platform a wide set of protection solutions ranging from bit parity to ECC techniques to advanced proprietary solutions. This technology also includes a fast and versatile engine that automates the memory protection process and searches for low-cost error correction architectures. For an SoC with more than 100 memories, 50% of which need to be protected, designers adopting M-RoCKIT will reduce the design time by 4 times. This full protection is achieved while saving from 15% silicon overhead for non-maskable memories and up to 8 times for maskable ones. These proprietary solutions drastically reduce the speed penalty as well. "This is the first commercially available tool in the field of memory bit flips protection. We strongly believe that this new type of Infrastructure IP will free fabless or IDM (1) See identity management. (2) (Integrated Device Manufacturer) A company that performs every step of the chip-making process, including design, manufacture, test and packaging. Examples of IDMs are Intel, AMD, Motorola, IBM, TI and Lucent. companies from a new, critical nanometer design risk in meeting the reliability specifications of their customers," said Eric Dupont, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of iRoC Technologies. iRoC Memory Protection Design Approach Bit flip occurrence is now a production concern for 0.13 um technologies and current FIT (Failure In Time) rates do not apply anymore to actual customer needs for security, reliability and availability. As an example, system houses demand a certain soft error rate (SER Ser serine. Ser abbr. serine SER smooth endoplasmic reticulum. Ser serine. ) for SoCs and memories within their procurement The fancy word for "purchasing." The procurement department within an organization manages all the major purchases. process that is impossible to reach without bit flip protection. Though ECC is a standard technique used by designers to protect memory or other devices, applying it "as is" in a complex SoC could add a significant cost burden and strap down performance. iRoC's Advisor with 25 ECC architectures, included within M-RoCKIT, identifies and decides the optimized protection architecture to meet memory specifications and acceptable ECC impact in terms of area, performance and power consumption. M-RoCKIT's versatile ECC generation engine operates at the RT level and uses a simple set of instructions to embed em·bed also im·bed v. em·bed·ded, em·bed·ding, em·beds v.tr. 1. To fix firmly in a surrounding mass: embed a post in concrete; fossils embedded in shale. and interconnect the correction block and its associated memory. "We are making the fully tested M-RoCKIT available now to give our customers and prospective alliance partners time to plan for incorporating this unique technology into their upcoming advanced designs as soon as possible," added Dupont. Availability The M-RoCKIT data sheet is available today on www.iroctech.com. The beta version will be available for selected customers and alliance partners within Q1/03 while final product pricing and delivery will be within the first half of 2003. About iRoC Technologies iRoC is The inaugural International Race of Champions was held at two tracks over two weekends in 1973 and 1974. The first three races were held October 27th and 28th at Riverside International Raceway and the final race was held on the Daytona International Speedway road course on February 14, a semiconductor intellectual property (IP) company that licenses design solutions to completely stop unreliability trends and increasing of FIT rates of nanometer processes. iRoC offers a turnkey and total solution from technology process characterization, a family of Infrastructure IP building blocks for Robustness, along with their tool suite, and radiation test services for dies or systems qualification. More information on the company's products and services can be obtained at www.iroctech.com. Note to Editors: iRoC Technologies and M-RoCKIT, are registered trademarks of iRoC Technologies Corporation. All other company or product names may be trademarks of the respective companies with which they are associated. |
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