iRoC Announces New BIST Tool for Memories; M-BISTeR Achieves a Breakthrough in Quality and Yield Enhancement.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Feb. 25, 2003 iRoC Technologies, a leader in the field of Semiconductor Infrastructure IP, announced today the release of M-BISTeR(TM), a new design tool for test, diagnosis and repair of defects in embedded Inserted into. See embedded system. memories. Advanced, unique cost-effective programmability features are combined with self-repair and versatile diagnosis capabilities to enable engineers to significantly improve the quality and reliability of new generations of memories. M-BISTeR is a turnkey solution that will be used by: -- Design engineers to embed em·bed also im·bed v. em·bed·ded, em·bed·ding, em·beds v.tr. 1. To fix firmly in a surrounding mass: embed a post in concrete; fossils embedded in shale. memory BIST BIST - Built-in Self Test in their SoC at a lower silicon cost -- Test engineers to achieve higher fault coverage through address, data and algorithm programmability -- Process quality and yield engineers to increase memory yield through self-repair without the need for laser repair operations The Need for Programmability Maintaining high SoC quality for nanometer technologies is a big challenge because increasingly complex defects in embedded memories cannot be detected by standard BIST solutions. Other issues include unaffordable un·af·ford·a·ble adj. Too expensive: medical care that has become unaffordable for many. un test costs, a huge technology debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users. time frame, yield losses and numerous customer returns. The traditional fault models such as "stuck-at," transition and coupling are not sufficient to guarantee appropriate fault coverage when designing 10X more transistors on a chip because exotic defects will throw a spanner in the work of yield and test engineers. These new defects are barely known and not yet modeled; therefore, test engineers must have full control of BIST in the SoC to adjust the test algorithm increasing the fault coverage. Programmability in BIST is now a must to assure high quality in nanometer technologies. "With our new versatile BIST technology, test engineers for the first time are able to synthesize To create a whole or complete unit from parts or components. See synthesis. any type of test algorithms on silicon in conjunction with efficient diagnosis and repair capabilities," said Michael Nicolaidis, chief technical officer of iRoC Technologies. iRoC's Quality, Yield and Reliability Methodology To develop a new memory technology, the first step is to implement programmable BIST, including diagnosis features to check a large number of different test algorithms and to determine the one that offers the highest fault coverage. During production ramp-up data collection using diagnosis is enabled to catch and analyze the few remaining defects. Diagnosis capability offers new defect analysis (programming) defect analysis - Using defects as data for continuous quality improvement. Defect analysis generally seeks to classify defects into categories and identify possible causes in order to direct process improvement efforts. and the test engineer can adjust and program a new test algorithm on the fly without new silicon revisions. At the same time, M-BISTeR's Built-in Self Repair feature enables the engineer to increase the yield without adding any time-consuming laser repair operation. Once the first chip lots are shipped, M-BISTeR still works. Its transparent BIST will test and detect defects when installed in field applications, thereby increasing the system reliability. Customer returns can be analyzed and the test algorithm can be adjusted using the unique programmability feature. Finally, the most efficient BIST can be synthesized and wired on the next lots to significantly decrease the BIST area cost and increase the production margin. "This unique methodology is possible because of the very low silicon cost of using our programmable BIST, which takes 10 to 15% less area than standard wired BIST. In addition, M-BISTeR can synthesize a fixed BIST for less than half the size of traditional BIST," emphasized Eric Dupont, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of iRoC Technologies. Availability M-BISTeR is available for shipping in April in North America North America, third largest continent (1990 est. pop. 365,000,000), c.9,400,000 sq mi (24,346,000 sq km), the northern of the two continents of the Western Hemisphere. and Europe. M-BISTeR will be sold as a tool with different options depending on customer needs for Built-in Self Test Built-in Self Test - (BIST) The technique of designing circuits with additional logic which can be used to test proper operation of the primary (functional) logic. , Built-in Self Repair and Built-in Self Diagnosis. About iRoC Technologies iRoC Technologies develops and licenses design and test solutions to enhance the security, quality and reliability of nanometer integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. . iRoC's turnkey solutions include technology process characterization, radiation test services and Semiconductor Infrastructure IP generators for SoC robustness and quality. More information on the company's products and services can be obtained at www.iroctech.com. Note to Editors: iRoC Technologies and M-BISTeR, are registered trademarks of iRoC Technologies Corporation. All other company or product names may be trademarks of the respective companies with which they are associated. |
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