iCODING's DVB-RCS Turbo Code Core Boosts Broadband Satellite Communications.

Business Editors/High-Tech Writers

SAN DIEGO--(BUSINESS WIRE)--Dec. 20, 2001

Combination of New Xilinx FPGA and Turbo Codec Core Creates 35 Percent

Increase for Return Channel Broadband Access Via Satellite

iCODING Technology Inc. announced a new broadband DVB-RCS (Digital Video Broadcast -- Return Channel Satellite) compliant turbo decoder core that provides state-of-the-art Forward Error Correction (FEC) of up to 15 Mbits/sec on a Xilinx Virtex-II(TM) FPGA.

The core can be used for Digital Video Broadcast (DVB), satellite communications, wireless LAN, digital TV, cable modem, and xDSL systems.

iCODING's S2000 DVB-RCS Turbo Code core supports the new DVB-RCS standard (ETSI EN 301 790) that defines the return link for satellite based broadband interactive data services. iCODING is the first North American vendor to support the new Turbo Code FEC option, which provides a 35 percent increase in return channel efficiency over traditional concatenated coding schemes. The iCODING core enables rapid introduction of this technology into commercial systems furthering satellite's competitiveness with other broadband technologies.

"We are very excited about the interactive satellite market," said Brian Edmonston, iCODING's president. "With the throughput that is achievable using DVB-RCS on the uplink and DVB-S (Satellite) on the downlink, satellite providers can more than compete with traditional broadband providers for the 'last mile' solution."

The S2000 core is based on convolutional constituent codes and supports Quasi-Error-Free (QEF) performance on the return link. DVB-RCS is the second major standards body after 3G wireless to adopt convolutional-based turbo codes. These standards are adopting convolutional-based turbo codes because they outperform all other FEC techniques. The core is also expected to be compliant with the emerging DVB-RCT standard for two-way Internet delivery via DVB-T (Terrestrial).

Leveraging FPGA Flexibility

iCODING offers its S2000 intellectual property products to FPGA designers as ready to use, pre-tested cores through the Xilinx AllianceCORE and the Xilinx SignOnce IP License programs. These cores can be placed into Xilinx Virtex II and Virtex E FPGAs, allowing engineers to design, test, trouble shoot, and reconfigure leading-edge communication systems.

The use of FPGAs significantly reduces the time to test and develop wireless communications systems that must adapt to quickly changing broadband standards. This offers flexibility and savings that are typically not available with ASIC-based solutions. Datasheet information can be downloaded from the Xilinx IP Center Web site at: http://www.xilinx.com/products/logicore/alliance/icoding/icoding.htm).

S2000 Family of Turbo Codec Cores

The S2000 Family of Turbo Codec Cores also includes the S2001 DVB-RCS Encoder, capable of 95 Mbits/sec on a Xilinx Virtex-II. The S2002 DVB-RCS Encoder and Decoder integrated and highly programmable. The S2100 DVB-RCT Decoder capable of date rates up to 31 Mbits/sec. The entire family achieves Quasi-Error-Free Performance, supports multiple modulation schemes, does not require external memory, and has low slice counts.

About iCODING Technology

iCODING produces high speed and high performance FEC cores, was founded in 1999 and is headquartered in San Diego. As a leader in Turbo Coding Technology, for wireline, satellite, and 3G applications, iCODING is an active participant in the IEEE 802.16 standard, and the ITU. For more information on iCODING and Turbo Codes, visit the Web site at: http://www.icoding.com.