eASIC Named Winner of the Prestigious EE Times' ACE Award for Ultimate Products in Logic and Programmable Logic Category.

SAN JOSE, Calif. -- A Stellar panel of industry technologists, educators and executives selected eASIC's breakthrough Structured eASIC Technology for its innovation and creativity

eASIC(R) Corporation, a provider of Configurable Logic and Structured ASIC products, today announced that its configurable logic product won the inaugural ACE (Annual Creativity in Electronics) Award presented by CMP Media's EE Times at the first annual awards gala held on March 9, 2005 as part of the Embedded Systems Conference in San Francisco, California. eASIC's innovative product was selected winner for Ultimate Products of the Year Award in the category of Logic and Programmable Logic, demonstrating leading edge technology and usability advantages.

"We are honored that our configurable logic product was selected by the engineering community as well as by industry experts as the Ultimate Logic Product," said Zvi Or-Bach, Founder and CEO of eASIC. "We are at an inflection point in the industry. The time has come for an innovative methodology that will cope with both cost and technology challenges of deep submicron designs. eASIC's technology uses a 'Standard Metal' approach, where all metal layers are standardized and the routing customization is done through a single via. Our maskless customization technique paves a unique NRE-free ASIC approach, eliminating custom mask-sets cost, allowing wafer-sharing and removing the barrier for new ASIC designs. Together with our world class strategic partners, including Flextronics Semiconductor, we are eager to serve the electronics engineering community and once again enable mass innovation through affordable logic customization."

Innovative Configurable Logic Technology - Structured eASIC

eASIC has a unique Configurable Logic technology implemented in its Structured eASIC products. The patented architecture consists of SRAM-based logic cells and flip-flops that are interconnected by a segmented wiring grid utilizing upper metal layers. The logic cells programming is done similarly to an FPGA, by loading a bit-stream to program the LUTs (Look-up-Tables) and initialize the flip-flops after powering up the device. The routing and interconnection is performed similar to other ASICs, but utilizes just a single via-layer for customization. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and a single custom Via-mask for customizing the routing. Moreover, the single mask can be eliminated for prototyping and low-volume by using Direct-write eBeam. Hence, eASIC's use of maskless lithography removes the customization tooling cost, shortens time-to-market, and adds manufacturing flexibility, allowing eASIC to provide the industry with an NRE-Free customized ASIC devices with densities, power and performance akin to a standard cell ASIC.

About eASIC

eASIC(R) has developed a breakthrough Configurable Logic technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. Its Structured eASIC architecture enables rapid and low-cost ASIC and SoC (System-on-Chip) designs by innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.

eASIC Corporation is a privately held company, Venture Capital backed by Kleiner Perkins Caufield and Byers. Headquartered in San-Jose, California, eASIC was founded in 1999 by Zvi Or-Bach, the founder of Chip Express.

www.eASIC.com