Zero Capacitor Memory Technology Proved Realisable on FinFET/TriGate Device Geometries; Highest Density Memory Provider Proves sub-45nm Capability.SANTA CLARA, Calif. & LAUSANNE, Switzerland -- A new paper presented by Mikhail Nagoga, senior device engineer with Innovative Silicon Inc. (ISi) at the IEEE's SOI (Silicon On Insulator) A chip architecture that increases transistor switching speed by reducing capacitance (build-up of electrical charges in the transistor's elements), and thus reducing the discharge time. The power requirement is also reduced in some designs. Conference in Honolulu; claims to prove the manufacturability of its Z-RAM(TM) (zero capacitor) embedded memory technology in FinFET and TriGate devices with geometries below 45nm. Z-RAM memory arrays have already been successfully demonstrated on silicon using partially depleted SOI structures, and the experimental results presented in ISi's new paper ensure that the technology will scale to 45nm and beyond. In the recently-introduced Z-RAM floating body memory cell, the conventional storage capacitor is replaced by the body capacitance of a SOI MOSFET (Metal Oxide Semiconductor Field Effect Transistor) The most popular and widely used type of field effect transistor (see FET). MOSFETs are either NMOS (n-channel) or PMOS (p-channel) transistors, which are fabricated as individually packaged . The charge stored in the floating body affects the device threshold voltage through the body effect and can be used to distinguish two states. This eliminates the need for a capacitor element, so the resulting memory cell structure is based solely on a single transistor. Therefore, Z-RAM memories can achieve five times the density of embedded SRAM See static RAM. SRAM - static random-access memory and twice the density of embedded DRAM designs. For the first time, new experimental work by ISi - presented in this IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. paper co-authored by ISi's CTO (Chief Technical Officer) The executive responsible for the technical direction of an organization. See CIO and salary survey. Pierre Fazan and personnel from TI, Infineon, SOITEC and ATDF ATDF American Tap Dance Foundation ATDF Advanced Technology Development Facility, Inc (Austin, TX) ATDF ASCII Test Data Format (semi-conductor industry) ATDF Automated Target Data Fusion (a subsidiary of Sematech) - shows that good retention characteristics for a Z-RAM memory cell based on CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. FinFET and Tri-Gate devices can be measured. This means that FinFET-based Z-RAM memories are manufacturable, enabling the production of very low cost DRAMs and eDRAMs for 45 and sub 45-nm generations. Comments Pierre Fazan: "This summer the first silicon we received back from the foundry has successfully demonstrated our claims for the Z-RAM technology on SOI. This new work shows that the structure is highly scaleable and suitable for use in devices for the years ahead." About Innovative Silicon Incorporated in 2002, Innovative Silicon was founded to develop and commercialise Floating Body effect memory for SoC/MPU products used in diverse applications including handheld computers, games consoles, cellular communications devices, cameras. The company closed its first round of VC funding in 2003, taped out its first 90nm megabit Z-RAM memory in 2004 and completed 65nm designs in July 2005. The company is incorporated in the USA, with R&D in Lausanne, Switzerland. www.z-ram.com |
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