Zarlink Semiconductor Standardizes On Synopsys' Physical Compiler Solution in Design Flow.Business Editors/High-Tech Writers MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--June 11, 2001 Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ) today announced that Zarlink Semiconductor(TM) (formerly Mitel Semiconductor) has integrated Synopsys' Physical Compiler(TM) into its standard design flow for .18 micron and below digital designs. In its first use of Physical Compiler, Zarlink realized substantial performance gains and reduced time to market for a complex design: a 500K gate system-on-a-chip with 35 memories, operating at 140 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. . The design flow previously used by Zarlink involved wireload model-based synthesis followed by place and route. To improve the design process, Zarlink teamed with Synopsys to adopt Physical Compiler into its timing closure flow. With just over one week of startup effort, Zarlink achieved the target circuit performance and successfully taped out on time. "Zarlink is constantly pushing the limits of circuit design to offer strategic differentiation to our customers," said Dennis Lewis, manager, design implementation and capability, Zarlink Semiconductor. "By using Synopsys' Physical Compiler we met our time-to-market target by completing the design in less than a month. Based on this success, it was an easy decision to incorporate Synopsys' Physical Compiler in our standard design flow." "I am excited to see the standardization of Synopsys' Physical Compiler by a technology leader such as Zarlink," said Sanjiv Kaul, senior vice president and general manager, Physical Synthesis Business Unit, Synopsys. "We are pleased to see that Zarlink was able to close the design in less than one month. The performance boost that Zarlink has seen builds upon the success that Synopsys' Physical Compiler has continuously demonstrated through more than a 150 tapeouts of communications, computing, graphics, and networking chips." About Physical Synthesis Pioneered by Synopsys, Physical Synthesis helps designers address the challenges of implementing next-generation system-on-a-chip designs. Synopsys' overall design flow includes Chip Architect design planner, Physical Compiler(TM) unified synthesis and placement, and FlexRoute top-level router. Synopsys' Physical Synthesis leverages industry-standard tools such as Design Compiler(TM), Module Compiler(TM), PrimeTime(R), Power Compiler(TM) and DFT DFT - discrete Fourier transform Compiler. Proven interfaces to third-party solutions allow the products to plug easily into an existing design flow. About Zarlink Semiconductor Zarlink Semiconductor employs its formidable analog, digital and mixed-signal capabilities to offer the most compelling products for wired, wireless and optical connectivity markets and ultra low power An ultra low power, or ULP device, is an electronic gadget that has milli- or micro-watt power consumption. Some examples of ultra-low power devices:
New York, Middle Atlantic state of the United States. It is bordered by Vermont, Massachusetts, Connecticut, and the Atlantic Ocean (E), New Jersey and Pennsylvania (S), Lakes Erie and Ontario and the Canadian province of and Toronto stock exchanges Toronto Stock Exchange (TSE) Canada's largest stock exchange, trading approximately 1,200 company stocks and 33 options. under the ticker symbol Ticker Symbol An arrangement of characters (usually letters) representing a particular security listed on an exchange or otherwise traded publicly. When a company issues securities to the public marketplace, it selects an available ticker symbol for its securities which investors "MLT (MultiLink Trunking) See port aggregation. " until the new legal name of the company -- Zarlink Semiconductor Inc. -- is approved by shareholders. For more information visit www.zarlink.com. About Synopsys Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, Calif., creates leading electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services support services Psychology Non-health care-related ancillary services–eg, transportation, financial aid, support groups, homemaker services, respite services, and other services to simplify the overall IC design process and accelerate time to market for its' customers. Visit Synopsys at http://www.synopsys.com. Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. Physical Compiler, Design Compiler, Module Compiler, and Power Compiler are trademarks of Synopsys, Inc. Zarlink is a trademark of Mitel Corporation. All other trademarks are the prosperities of their respective owners. |
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