ZSP Demonstrates 400 MIPS Superscalar DSP Operating at 200 MHz.

TORONTO--(BUSINESS WIRE)--Sept. 14, 1998--

ZSP Corporation (ZSP) demonstrated the 200 MHz ZSP16401, a high-performance, 16-bit fixed-point digital signal processor (DSP) at DSP World Expo today.

This 400 MIPS superscalar DSP is the first device based on the ZSP 10X DSP(TM) architecture. Designed specifically for the communications infrastructure market, the ZSP16401, which is available for sampling now, provides a breakthrough in the level of performance, several times what is available using most conventional DSP architectures.

It also reduces cost and power consumption, since fewer chips are needed in digital communications applications. This device combined with its optimized C compiler allows engineers to design the advanced next generation applications quickly by reducing the amount of time required for software development.

Originally announced in February of this year, ZSP's first silicon in 0.35um emphasized functionality over speed, allowing initial customers to evaluate and develop software. By migrating to a 0.25um process and substituting a higher performance library, ZSP has been able to achieve their target operating frequency of 200 MHz in only nine months with one additional mask set. This leaves open the possibility of further performance enhancements with 0.18um or smaller geometries.

"Demonstrating 200 MHz in a commercially available portable 0.25um process validates our premise that RISC-based architectures are the future of DSP," said Michael Morrissey, CEO of ZSP Corporation. "The ZSP16401 not only enables customers to meet the performance requirements of next-generation communications systems, but also enables system designs that were previously only feasible with hard-wired logic, to be realized now in software using our DSP."

400 MIPS Enables Next-Generation Systems

Next generation communications infrastructure equipment requires high performance for multichannel applications, low cost-per-channel and power efficiency. The ZSP16401 satisfies these needs by utilizing a powerful, yet flexible RISC (reduced instruction set) architecture that provides 400 DSP MIPS at 200 MHz. At the same time, it consumes less than 2W.

The device can perform two 16-bit MAC operations with 40-bit result for an aggregate of 400 million MAC operations per second. Furthermore, it has the ability to perform a high precision (32-bit) MAC operation with a 40-bit result, or an add-compare-select for Viterbi decoding in a single-cycle and can execute a complex multiply in two cycles.

As a result, this device enables designers to use DSPs to comply with increasingly complex digital standards (i.e. W-CDMA, Enhanced Data rates for GSM Evolution ((EDGE)), etc.), to realize more complex algorithms such as interference cancellation or smart antennas to increase system capacity, and to reduce system costs by integrating more channels per DSP. As an example, the processor can process 12 channels of G.729 and echo cancellation simultaneously.

Price and Availability

The 200 MHz ZSP16401 is available in both 28x28mm PQFP and 17x17mm LBGA packages. It is currently sampling to select customers and will begin general sampling in October 1998, with production to follow in 1Q99. Pricing is $50.00/$10,000. For additional product information, OEMs should contact Kevin Stone at 408/986-1686.

ZSP Corporation develops high-performance, low-cost digital signal processor devices. Founded in March of 1996, the company's headquarters are in Santa Clara, California. ZSP Corporation, 982 Walsh Avenue, Santa Clara, CA 95050-2649. Tel: [phone] Fax: [phone] E-mail: [e-mail]. On the Web: http://www.zsp.com.

Note to Editors: 10X DSP(TM) is a trademark of ZSP Corporation. All other names mentioned are trademarks, registered trademarks or service marks of their respective companies.

CONTACT: ZSP Corporation, Santa Clara

Kevin Stone, 408/986-1686

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or

BW&A Public Relations

Donna Buckmaster-Wilson, 510/795-0111

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