Xilinx provides proven XAUI solution for 10 Gigabit Ethernet applications.
Xilinx, Inc. (Nasdaq:XLNX) has announced that it has successfully completed the University of New Hampshire Interoperability Lab (UNH IOL IOL Intraocular lens, see there ) IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 802.3 conformance tests for 1 and 10 Gigabit Ethernet Media Access Controller (MAC). Xilinx also announced successful interoperability testing of its 10 Gigabit Attachment Unit Interface See AUI.
(networking) Attachment Unit Interface - (AUI) The part of the IEEE Ethernet standard located between the MAC, and the MAU. The AUI is a transceiver cable that provides a path between a node's Ethernet interface and the MAU. (XAUI XAUI 10 Gigabit Attachment Unit Interface
XAUI Extended Auxiliary Unit Interface
XAUI XSBI Attachment Unit Interface (IEEE 802.3ae)
XAUI Ten Gbps Attachment Unit Interface ) IP core with a number of 3rd party vendors during several group test sessions. In addition, Xilinx also announced two new IP cores today, the XAUI and Ethernet 1000BASE-X PCS/PMA LogiCORE products. Both cores are available now for use with Virtex-II Pro Platform FPGAs. The two new IP cores further extend Xilinx's serial interface IP offering, part of the comprehensive suite of design resources under the Serial Tsunami initiative.
"The flexibility of Xilinx Platform FPGAs enabled Xilinx to complete the Ethernet MAC conformance testing with a surprisingly short test cycle," said Bob Noseworthy, 10 Gigabit Ethernet Consortium Manager at UNH IOL. "Xilinx's in-house Ethernet expertise worked to deliver a solid and robust 10 Gigabit Ethernet solution."
By successfully completing the UNH IEEE 802.3 conformance tests for Ethernet MAC and by demonstrating interoperability with networking equipment incorporating standard gigabit Ethernet devices, Xilinx is providing IP solutions that significantly reduce the hardware testing burden for customers and accelerate their time to market. In addition, Xilinx' participation in three XAUI group tests has resulted in an extensive portfolio of XAUI devices with which the Virtex-II Pro FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. using the XAUI IP core can interoperate. Customers using Virtex-II Pro FPGAs and Xilinx 1 & 10 Gigabit Ethernet IP cores are ensured first time design success and seamless operation with other 1 & 10 Gigabit Ethernet standard devices in their networking and telecommunication systems.
The new 1000BASE-X PCS/PMA and XAUI cores can be used in the development of emerging 1 & 10 Gigabit networking and telecom equipment. Both cores are parameterizable and customizable via the Xilinx CORE Generator software. The 1000BASE-X core is designed to the IEEE 802.3-2002 standard, and is available with a choice of two PHY side interfaces: a 1000BASE-X PCS with Ten Bit Interface (TBI TBI 1. Thyroxine-binding index 2. Total body irradiation ), or an integrated 1000BASE-X PCS/PMA which allows designers to simplify their board designs. The XAUI core utilizes four channel-bonded Virtex-II Pro RocketIO transceivers to provide a 4-lane high-speed serial interface The High-Speed Serial Interface (HSSI) is a differential ECL serial interface standard developed by Cisco Systems and T3plus Networking primarily for use in WAN router connections. It is capable of speeds up to 52 Mbit/s with cables up to 50 feet in length. offering 10 Gigabits per second (Gbps) total data throughput. Included with the XAUI core are the XGMII XGMII 10 Gbit Media Independent Interface
XGMII Ten Gbps Media Independent Interface Extender Sublayers (DTE and PHY XGXS) and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3ae-2002. Both cores can be used in bridging applications to transfer Ethernet frames across non-Ethernet media when protocol termination is not required. In addition, free FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods.
FIFO - first-in first-out design examples are available now for current GMAC & 10GMAC customers providing full line rate support for back-end user logic.
The Ethernet 1000BASE-X PCS/PMA and XAUI cores are available now as LogiCORE products under the terms of the SignOnce IP license and are downloadable from www.xilinx.com/connectivity. The site license price for the 1000BASE-X PCS/PMA core is $5000, while the XAUI core is provided free of charge. Both cores are available for use in Virtex-II Pro Platform FPGAs using ISE Ise (ē`sā), city (1990 pop. 104,164), Mie prefecture, S Honshu, Japan, on Ise Bay. It is one of the foremost religious centers of Shinto, the site of the shrines of Ise. 5.2i with Service Pack 2 or later revision software. Free user-side FIFO design examples are available for download in the respective product lounges for current 1 & 10 GMAC licensee customers.