Xilinx introduces new Xilinx-Synopsys interface and libraries; new interface dramatically improves FPGA synthesis and simulation.

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 16, 1995--Xilinx Inc. (NASDAQ:XLNX) Monday announced a new release of its Xilinx-Synopsys Interface and Libraries (XSI) for the Xilinx XC3000 and XC4000 families of field programmable gate arrays (FPGAs), and the Xilinx XC7000 family of erasable programmable logic devices (EPLDs).

The new XSI, version 3.2, offers design engineers significant new enhancements for speeding the design process and producing higher quality results.

"HDL-based design results using Synopsys' FPGA Compiler are now within 10 percent of schematic-based results," said Hans Schwarz, director of Xilinx's Software Marketing.

"High-level design tools from Synopsys Inc. in the areas of synthesis, simulation and design re-use complement the Xilinx programmable logic device solutions. Together, the two companies offer the ideal solution for reducing time-to-market in electronic system design."

"The XSI release is a major milestone in our new five year partnership announced last January," said Jan Anderson, director of the Synopsys Semiconductor Vendor Program.

"Xilinx has demonstrated their commitment to a new way of designing FPGAs and EPLDs by supporting Synopsys synthesis and simulation technologies. They have also proven to be one of our most customer-oriented partners by providing customers with complete solutions, including application notes and training."

XSI version 3.2 contains several significant improvements and additions:

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-- New synthesis libraries offer timing estimates that match post-layout results within plus or minus 10 percent

-- Improvements to design flows allow automatic I/O insertion and seamless integration with XACT 5.x

-- New Synopsys VHDL System Simulator libraries provide complete verification of designs after layout

-- New XC7000 series EPLD libraries allow design using the same high level design flow as FPGAs.

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XSI version 3.2 offers a complete and optimized solution from design concept through verification through new simulation models. Available for the XC3000, XC4000 and XC7000 families, the simulation models provide full timing and gate-level simulation after layout, using the Synopsys VHDL System Simulator (VSS). The gate-level accelerator present in VSS dramatically reduces simulation time up to 75% while increasing accuracy.

"The addition of gate-level simulation models for the Synopsys VHDL System Simulator to the Xilinx-Synopsys interface was a major improvement for us," said Ivan Lee, senior design engineer at Efficient Networks Inc. "The VSS models gave us a complete design solution and allowed us to remain completely within the Synopsys environment. This significantly improved our system debugging time."

Expanded synthesis libraries for the Xilinx XC3000 and XC4000 FPGA families allow fully automatic insertion of most types of I/O pad cells including registered, latched, and bi-directional I/O pads. More accurate wire load models are included for all supported devices and speed grades.

When using the FPGA Compiler for the XC4000 family of FPGAs, synthesis timing estimates are within 10 percent of actual post-route delays.

Complete libraries and user documentation for users of both Synopsys Design Compiler and FPGA Compiler are included with the XSI version 3.2. FPGA Compiler users targeting the XC4000 family of FPGAs can expect a 30 percent or higher reduction in design area compared to Design Compiler results.

Xilinx has extended its Synopsys support to include the XC7000 family of EPLD devices with complete synthesis, DesignWare, and VSS simulation libraries. The DesignWare library allows users to take full advantage of the advanced XC7000 architecture. The VSS simulation library supports both functional and post-implementation gate-level timing simulation.

Pricing and Availability

The Xilinx-Synopsys Interface version 3.2 is now shipping free of charge to current XSI users on maintenance and is available for purchase by new customers. List price for the Xilinx-Synopsys Interface is $3,995 when purchased alone, and $9,995 when purchased with a complete XACT 5.0 software development system. Supported platforms include: Sun-4, HP Series 700, and IBM RS-6000 workstations.

Company Backgrounds

Synopsys Inc. (NASDAQ:SNPS) develops, markets, and supports high-level design models and software for designers of integrated circuits (ICs) and electronic systems. The company pioneered the commercial development of synthesis technology, which serves as the foundation of the company's high-level design methodology.

Synopsys currently offers a comprehensive set of synthesis, simulation, test, and design reuse solutions, which support both Verilog HDL and VHDL.

Founded 10 years ago, Xilinx is the world's leading supplier in the billion dollar CMOS programmable logic industry. The company pioneered the market for field programmable gate arrays (FPGA), semiconductor devices that provide high integration and quick time-to-market for electronic equipment manufacturers in the computer peripherals, telecommunications, industrial control, instrumentation, and military markets. Headquartered in San Jose, the company produces innovative device architectures and associated development system software.

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Note to editors; Xilinx, XC3000, XC4000, and XC7000 are trademarks of Xilinx, Inc. Other trademarks are owned by their respective companies.

CONTACT: Xilinx, Inc.

Vallee Hubbard, 408/879-5085