Xilinx delivers industry's fastest microcontroller with new PowerPC-based UltraController-II reference design.Xilinx, Inc. (Nasdaq:XLNX) has announced immediate availability of the UltraController-II microcontroller reference design that provides a high performance, logic-optimized solution based on the industry standard PowerPC 405 processor immersed in Xilinx Virtex Platform FPGAs. With emphasis on ease of use, the ultra-compact, general-purpose controller A peripheral control unit that can service more than one type of peripheral device; for example, a printer and a communications line. applies patent-pending innovations to more than double the original UltraController performance with operating frequencies up to 400 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. in Xilinx Virtex-II Pro and 450 MHz in Virtex-4 FX devices. The new design also reduces logic resource utilization by over one fifth that of the original UltraController design with four times lower power consumption than competing soft core implementations. The UltraController-II reference design is a pre-configured and verified processing engine with 32 bits of user-defined general-purpose input and output (GPIO GPIO General Purpose Input/Output GPIO General Purpose Input Output ) that can interface to logic internal or external to the FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. without using valuable FPGA resources. Operating at the maximum clock frequency of the PowerPC 405 core, the new design loads and executes code exclusively from the integrated PowerPC 16KB instruction and 16KB data cache memory. This innovative approach eliminates the need for block RAM resources and accelerates program instruction and data access with faster code execution. The entire UltraController-II design is achieved with a minimal footprint that occupies only ten logic cells to free up FPGA logic for more value-added functions. The production-ready design can be easily fielded by programming the FPGA from PROM or Xilinx-compatible devices. "The original UltraController design was a key element in the rapid development of our UTS (Universal Timesharing System) Amdahl's version of Unix System V. Release 4.0 is POSIX compliant. series of advanced Ethernet Transport products. Since the UltraController-II code is stored in cache, faster, more complex state machines can be migrated from traditional gate/ register-based state machines to software based implementations. Further, the new support for an interrupt, timers and general purpose I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output greatly expands the capabilities," stated Bob Cantwell, director of ASIC/FPGA Engineering at Ceterus Networks. The UltraController-II feature set supports a variety of embedded functions including logic and data control, device configuration, system management and simple data manipulation Processing data. . New interrupt handling capabilities allow UltraController-II applications to perform high-speed, base level computation and handle time-critical events as they occur. Fixed interval and programmable interval timer In computing, a Programmable Interval Timer (PIT) provides one or more counters which trigger an interrupt when they reach their programmed count. Common Features PITs counters may be one-shot or periodic. One-shot timers interrupt only once, and then stop counting. resources enable commonly embedded tasks such as time-of-day computation, data-logging for system service routines, and periodic servicing of timesensitive external devices. In addition, a watchdog timer A clock circuit that keeps counting from a set number down to zero. If the event it is monitoring occurs before it reaches zero, it resets to the starting number and starts counting down again. monitors systems and eliminates upsets by issuing resets to aid in the recovery from system failures. "In today's competitive environment, embedded applications must be designed and verified faster than ever, despite increased complex system requirements," said Dan Isaacs, director of Embedded Processor Marketing, Advanced Products Division at Xilinx. "Xilinx provides a comprehensive range of processing solutions and pre-configured reference designs allowing customers to maximize their engineering resources. Building on proven acceptance of our UltraController approach, the new UltraController-II source code is compatible with the original design to provide existing users an easy migration path." UltraController-II applications are easily implemented and customized using the standard Xilinx ISE Ise (ē`sā), city (1990 pop. 104,164), Mie prefecture, S Honshu, Japan, on Ise Bay. It is one of the foremost religious centers of Shinto, the site of the shrines of Ise. and Platform Studio tool suites with a simplified design flow that bridges both hardware and software domains. The UltraController-II reference design is offered free of charge and immediately accessible for download at www.xilinx.com/ ultracontroller. It includes HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. source files and examples, C source code application examples, Application notes and QuickStart tutorial. A comprehensive suite of embedded development boards is also available from Xilinx and third-party companies. |
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