Xilinx announces free configurable PCS reference design for use with Virtex-II pro platform FPGAS.

Xilinx, Inc. (Nasdaq:XLNX) has announced the availability of a free fully functional Configurable Physical Coding Sublayer The Physical Coding Sublayer (PCS) further helps to define physical layer specifications for ethernet.

The Ethernet PCS sublayer is part of the Ethernet PHY layer. The hierarchy is as follows: (CPCS CPCS Common Part Convergence Sublayer
CPCS College of Public and Community Service (various universities)
CPCS Committee for Public Counsel Services (Massachusetts)
CPCS Check Processing Control System ) reference design for a multi-mode PCS (1) (Personal Communications Services) Refers to wireless services that emerged after the U.S. government auctioned commercial licenses in 1994 and 1995. This radio spectrum in the 1. block implemented in Xilinx Virtex-II Pro FPGAs. The CPCS can be dynamically configured to support three types of PCS layers including Fibre Channel (1.0625 and 2.125 Gbps), Gigabit Ethernet (1000BASE-X), and ESCON/SBCON (200 Mbps). The CPCS reference design is ideal for applications including Ethernet/Fibre Channel switches, Multi-Service Provisioning Platforms (MSPP (MultiService Provisioning Platform) A high-end Cisco router that supports TDM circuits, packets and optical connections at the edge of the network. See MSSP and MSTP. ), SONET/SDH terminals, Add-Drop Multiplexers (ADM), cross connects, CWDM/DWDM transport equipment, and IP routers.

"Designers using the CPCS reference design can dramatically reduce costs while improving time-to-market," said Amit Dhir, senior manager of Strategic Solutions, Wired Networks and Telecom, at Xilinx. "The reference design enables the sharing of optics and ICs and integrates the RocketIO MGT and PowerPC features of our Virtex-II Pro FPGAs. This provides increased density at each port, with the ability to be re-configured on the fly."

Dynamic protocol selection is fully integrated into the control plane running on the Virtex-II Pro embedded PowerPC 405 processor. The tight coupling of the configurable embedded RocketIO MGTs provide the required serial data rates ranging from 200 Mbps to 2.125 Gbps. This would not be feasible with an external SERDES See serializer/deserializer. solution.

COPYRIGHT 2004 Millin Publishing, Inc.
No portion of this article can be reproduced without the express written permission from the copyright holder.

Reader Opinion

Article Details
Printer friendly Cite/link Email Feedback
Publication:	EDP Weekly's IT Monitor
Article Type:	Brief Article
Geographic Code:	1USA
Date:	May 3, 2004
Words:	211
Previous Article:	EDO awarded contract for electronic equipment on EP-3E reconnaissance aircraft.
Next Article:	Unisys enhances ES7000.
Topics:	Semiconductor industry Product introduction

Related Articles
Xilinx and Tensilica announce configurable processor support for programmable systems design.
Xilinx announces next gen free ISE WebPACK 5.2I design tool for reduced design costs and increased productivity.(Integrated Software Environment...
Xilinx provides proven XAUI solution for 10 Gigabit Ethernet applications.
Xilinx Virtex-II Pro FPGAs Are 38% Faster Than Competitive Offerings Using ISE 6.1i Design Tools.
Xilinx delivers world's first FPGA-based DSP software tool with JTAG interface.
Xilinx and AMIRIX announce MultiBERT reference design for serial backplane validation.
Xilinx simplifies QDR II SRAM Memory interfacing with new Virtex-II Pro memory tool kit.
Xilinx shatters 2.4 terabit PICMG 3.0 bandwidth barrier by demoing 10Gbps serial signaling over ATCA backplane.(Advanced Telecom and Compute...
Xilinx intros next-gen EasyPath FPGAs priced below structured ASICs.(Field Programmable Gate-Array, Application Specific Integrated Circuit)
Xilinx delivers industry's fastest microcontroller with new PowerPC-based UltraController-II reference design.