Xilinx and PMC-Sierra Announce Availability of Interoperable SPI-4.2/POS-PHY Level 4 Solution with Dynamic Alignment.

Business Editors and Technology Writers

Communications Design Conference 2002

Booth #818

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 24, 2002

Xilinx's Single Chip Link Layer SPI-4.2 Interface to be

Demonstrated at Communications Design Conference

PMC-Sierra (Nasdaq:PMCS) and Xilinx, Inc. (Nasdaq:XLNX) today announced the successful completion of hardware interoperability testing between the Xilinx(R) Virtex-II series FPGA-based SPI-4.2/POS-PHY Level 4 (PL4) core with dynamic alignment and PMC-Sierra's XENON(TM) family of OC-192 and 10 Gigabit Ethernet physical layer devices.

The most recent set of interoperability tests with Xilinx's SPI-4.2/PL4 (V5.0) core represent the first commercially available bi-directional dynamic alignment SPI-4.2/PL4 solution. SPI-4.2/PL4 interfaces with dynamic alignment can automatically detect and compensate for trace-length differential which significantly simplifies the PC board layout and provides system designers with a robust system interface that will reduce their overall design cycle and cost.

"PMC-Sierra and Xilinx have worked closely for nearly two years now to ensure hardware interoperability between our solutions at 10 Gbit/s rates," said Steve Perna, vice president and general manager of PMC-Sierra's Service Provider Division. "PMC-Sierra's XENON devices have been demonstrating dynamic alignment functionality since our initial delivery in 2001. We are now very pleased to be able to offer, along with Xilinx, the industry's first proven dynamic alignment solution."

"Thanks to our close relationship with our semiconductor alliance partner, PMC-Sierra, we are able to demonstrate and deliver the industry's first commercially available SPI-4.2/PL4 solution with bi-directional dynamic alignment," said Jerry Banks, director of Xilinx Global Alliances. "Hardware interoperability with PMC-Sierra's leading physical layer solution, along with single chip dynamic alignment, makes designing with SPI-4.2/PL4 interfaces significantly easier, resulting in reduced PC board layout complexity."

Dynamic alignment compensates for variations in data path trace-lengths, reducing PC board layout complexity especially in modular systems when multiple line-cards might interface to the same mother card.

PMC-Sierra and Xilinx originally demonstrated interoperability with Xilinx's SPI-4.2/PL4 core in December 2001 (see December 17, 2001 press release). PMC-Sierra's XENON devices with dynamic alignment SPI-4.2/PL4 technology have been shipping in volume since August 2001. Xilinx's single-chip link-layer dynamic alignment SPI-4.2/PL4 interface will be demonstrated at the Communications Design Conference, September 23-26 at the San Jose Convention Center, booth #818.

About SPI-4.2 /POS-PHY Level 4 Standard

POS-PHY Level 4 originated from the SATURN(R) Development Group, co-founded by PMC-Sierra in 1992. It has since been standardized in the OIF as System Packet Interface Level 4 Phase 2 (SPI-4.2) and in the ATM Forum as Frame-Based ATM Interface Level 4 (FBATM-4). SPI-4.2/ PL4 is an industry standard multi-service system interface supporting OC-192, 10 Gigabit Ethernet and multi-channel configurations, including 2.5 Gbit/s OC-48, 622 Mbit/s OC-12 and Gigabit Ethernet, as required by the new generation of super routers and Layer 3 switches used in multi-service voice and data networks. The interface is flexible, supporting high-speed Packet-over-SONET (POS) Internet traffic as well as 10 Gigabit Ethernet, Gigabit Ethernet and Asynchronous Transfer Mode (ATM) applications. For more information, visit http://www.pmc-sierra.com/posphylevel4.

License Price and Availability

The fully configurable, multi-channel, SPI-4.2/PL4 LogiCORE module is available now for use with the Xilinx CORE Generator System. Pricing for the core is $18,000. Licensing information and instructions for downloading the core as well as information on all Xilinx LogiCORE(TM) products can be found at http://www.xilinx.com/ipcenter. The SPI-4.2/PL4 core is licensed under the terms of the SignOnce IP License, a single set of terms for licensing FPGA-based IP cores from Xilinx and over 25 third-party providers. For more information visit http://www.xilinx.com/ipcenter/signonce.htm.

About Xilinx

Xilinx, Inc. (Nasdaq:XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at http://www.xilinx.com.

About PMC-Sierra

PMC-Sierra is a leading provider of high speed broadband communications semiconductors and MIPS-based processors for Enterprise, Access, Metro Optical Transport, Storage Area Networking and Wireless network equipment that makes up the backbone of the Internet. The company offers worldwide technical and sales support, including a network of offices throughout North America, Europe and Asia. PMC-Sierra is included in the S&P 500 Index which consists of 500 stocks chosen for market size, liquidity, and industry group representation and in the NASDAQ-100 Index (NDX) which contains the largest non-financial companies on the NASDAQ Stock Market. The company is publicly traded on the NASDAQ Stock Market under the PMCS symbol. For more information, visit http://www.pmc-sierra.com.

(c)Copyright PMC-Sierra, Inc. 2002. All rights reserved. SATURN(R)is a registered trademark of PMC-Sierra, Inc. PMC-Sierra(TM)and XENON(TM)are trademarks of PMC-Sierra, Inc. All other trademarks are the property of the respective owners.