Xilinx Unveils New FPGA Architecture to Enable High-performance, Ten Million System-Gate Designs; New Virtex-II Architecture Delivers Twice the Performance of Virtex Family.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--May 22, 2000

Xilinx, Inc. (Nasdaq:XLNX), the leader in programmable logic solutions, today announced the next generation Virtex(TM) architecture representing the latest platform for the Virtex series -- an FPGA series that ushered FPGAs into markets and applications previously addressed only by ASIC solutions.

The new Virtex-II architecture will provide unprecedented amounts of memory resources and capabilities, new arithmetic resources, enhanced clock management support, new I/O technology, and the next-generation deep-submicron process technology. This architecture propels system performance to the next level, maximizing bandwidth in I/O, timing, memory, and processing. The first products of this ten million system-gate architecture will be available later this year.

"The Virtex series is the commanding platform of choice, holding over 90 percent of the market for advanced architecture FPGAs and the Virtex-II architecture builds on that legacy of innovation," said Dennis Segers, senior vice president and general manager for the Xilinx Advanced Products Group. "We furthered our leadership with the delivery of our version 3.1i software enabling ten million system-gate design. The Virtex-II architecture will be the hardware vehicle for this new density level and beyond."

State-of-the-art technology enhancements

Geared for 500 million-transistor complexity, the architecture is optimized for rapid migration to 100-nm process technology. Using eight-layer interconnect and employing copper technology, the enhanced configurable logic block (CLB) structure achieves an unprecedented combination of silicon efficiency, performance, and routability. CLB enhancements include easier look-up table (LUT) cascading, wide fan-in MUXes, deeper distributed RAM, and arbitrary length shift-registers.

System designers will realize twice the logic performance of the Virtex family at half the power. The Xilinx Active Interconnect(TM) technology, the fourth generation of Xilinx routing, boasts predictable high performance to simplify cores implementation and minimize place and route times in 10 million-gate designs. This architecture delivers consistent performance across a wide range of high fan-out outputs. This tight fan-out versus delay characteristic is crucial in maintaining very high performance in multi-million gate designs.

Software available now to remove the barriers of high-performance, high-density designs

Mega-density designs of tomorrow will require new design tools to achieve the highest productivity. The Alliance Series version 3.1i design flow has built-in enhancements, including modular design for teams of engineers working together, dramatic runtime improvements for timing closure, incremental design flows, and hierarchical floorplanning for designs of up to ten million gates. The new architecture was designed for ease of synthesis and to provide accurate post synthesis timing results. The new FPGA architecture is fully supported in this current Xilinx software release as well as from all leading synthesis tool partners.

The essential role of IP in ten million system-gate designs

Mega-density designs will require efficient and quick integration of multiple IP building blocks with ever-increasing complexity; the Virtex-II architecture was engineered with this need in mind. With the original Virtex series, Xilinx pioneered the use of Smart-IPTM technology, which enables high performance predictable and parameterizable cores. This technology allows predictable core performance through relational placement within the IP; the Xilinx Active Interconnect technology, new in the Virtex-II architecture, extends this predictability between IP blocks. The interconnect technology in concert with the modular design feature of the software allows multiple IP blocks to be efficiently integrated within mega-gate designs.

System features build high performance

System bandwidth: Xilinx pioneered the SelectI/OTM technology, which provides designers with the flexibility to choose any I/O standard on any pin at the full performance of the I/O standard. The Virtex-II architecture extends this capability to over 800 Mbit per second (Mbps) I/O performance. Additional support is provided for emerging industry standards, such as Rapid I/O used in communications applications.

High bandwidth memory hierarchy: This architecture represents the Xilinx fourth generation of SelectRAM(TM) memory hierarchy for high bandwidth applications. The SelectRAM hierarchy in the Virtex-II architecture enhances distributed RAM, doubles the block RAM, and increases the interface performance to external memory. The Xilinx distributed RAM blocks can be chained together, up to 128 deep, for fast content addressable memories (CAMs), register banks, and data caches, used in DSP pipelining applications. The memory blocks have increased four times since the Virtex family to 18 KB. Continuing with the unprecedented memory-to-logic ratio established in the Virtex-E and Virtex-EM families, this new architecture addresses the needs of next-generation data-intensive applications such as Internet infrastructure products. Building on the strength of the True Dual-Port(TM) memory, the new Virtex-II architecture also provides support for parity bits. New read-before-write and no output change-write modes have been added to enhance the processing capability of the logic/DSP fabric. In addition, this new architecture enables seamless memory interfaces to highest-performance DDR and QDR of over 300 Mbps with enhanced DDR I/O support.

Processing bandwidth: The new Virtex-II architecture significantly improves the arithmetic performance with embedded 18-bit multiplier capability, supporting over 0.6 Tera multiply and accumulate (MAC) performance levels crucial for real-time DSP performance in applications such as video and communications.

System timing bandwidth: With ever-increasing system performance, designers are faced with ever-decreasing timing margins and complex system clock management challenges. The Virtex-II architecture helps designers solve these challenges with enhanced global clock distribution and multiple digital delay locked loops (DLLs) running at over 400 MHz.

About Xilinx

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx Web site at www.xilinx.com.