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Xilinx Deploys Copper on Network Switch FPGA Family; New Virtex-E Extended Memory Family Supports 160 Gbps Buffered Cross-Bar Switches.


Business Editors & High-Tech Writers

SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, Calif.--(BUSINESS WIRE)--March 27, 2000

Xilinx, Inc. (Nasdaq:XLNX) today announced the Virtex(TM)-E Extended Memory (Virtex-EM) family, the company's newest family of FPGAs that provides greater block RAM and higher memory bandwidth Memory bandwidth is the rate at which data can be read from or stored into a semiconductor memory by a processor. Memory bandwidth is usually expressed in units of bytes/second, though this can vary for systems with natural data sizes that are not a multiple of the commonly used  for specific applications.

The Virtex-EM family is the first family to offer over one megabit of Xilinx(R) True Dual Port(TM) Block RAM and is also the first FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market.  available in the industry with copper interconnect to increase performance and minimize power consumption.

"Xilinx developed the Virtex-EM family to address application requirements identified primarily by our large networking customers," said Dennis Segers, senior vice president and general manager of the Xilinx High-End FPGA division. "The unique combination of block RAM and logic, along with copper interconnect, offer networking companies an architecture platform for their 160 Gbps switch fabrics. The high memory-to-logic-ratio content is also ideal for other data intensive applications such as high definition video imaging."

The Virtex-EM family significantly increases block RAM content and leverages the success of the Virtex-E family. Like its predecessor, the Virtex-EM architecture includes eight Delay Locked Loops (DLLs), distributed RAM, and a seamless interface to 20 voltage and signal standards, including LVDS (Low Voltage Differential Signaling) A transmission method for sending digital information. LVDS sends data over data high and data low lines rather than data and ground. , Bus LVDS, and LVPECL LVPECL Low Voltage Positive Emitter Coupled Logic  differential signaling Using two wires for each electrical path for high immunity to noise and crosstalk. The signals are sent down one wire as positive and the other as negative, and the circuit at the receiving end derives the signal from the difference between the two. .

"When we architect our products, we specifically look for places we can leverage the time to market and flexibility advantages of Xilinx FPGAs," said Satish Soman soman, colorless liquid used as a nerve gas. It boils at 167°C;, evolving an odorless vapor. It is rapidly absorbed through the skin; death may result within 15 min of exposure. In nonfatal concentrations it is hazardous to the eyes. , vice president of Chip Development, Core Routing Division, Lucent Technologies. "For our next generation products, the Virtex-E Extended memory devices have great potential in addressing unique needs of our resource management system."

Perfect for Network Switching Applications...

Industry-leading Virtex-E devices are used in communications, networking, and video and image processing applications, where the inherent flexibility of the architecture allows powerful data path and digital signal processing See DSP.

Digital Signal Processing - (DSP) Computer manipulation of analog signals (commonly sound or image) which have been converted to digital form (sampled).
 (DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive ) operations to be efficiently implemented.

Within these market segments, many applications can benefit from additional block memory used for FIFOs and buffers, which greatly enhance overall system bandwidth. For example, network systems using 160 Gbps buffered cross-bar switches can use the large on-chip memory of the Virtex-EM devices to combine all the individual FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods.

FIFO - first-in first-out
 memories as well as the interconnect logic on a single FPGA. This allows increased data bandwidth and greater integration.

"The Virtex-EM family represents another example of innovation we have come to expect from Xilinx," said Marion Rusu, manager of the hardware engineering group of the ATM division at Cisco Systems, Inc. "With the memory bandwidth possible, I definitely see a great future for these devices at Cisco."

...and High-end Video Processing Applications

Another example is high-end video processing, which use DSP engines to improve image quality and implement video compression and decompression algorithms. Traditionally, the video processing engine is implemented in either an FPGA or an ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor.  with an external line buffer memory to store eight pixel lines.

By using the large block RAM capacity of the Virtex-EM device, both the line buffer memory and either a video processing engine or a DSP function can be accommodated on the same device, which greatly enhances the overall system bandwidth.

First With Copper Process Technology

Over the past two years, Xilinx engineers have worked in close collaboration with United Microelectronics Corp. (UMC UMC United Methodist Church
UMC United Microelectronics Corporation
UMC University Medical Center
UMC United Microelectronics Corp (Republic of China)
UMC University of Missouri-Columbia
) toward the developed of the advanced copper process technology used to build the Virtex-EM family. The delivery of these devices marks the first availability of copper-based FPGAs.

The devices are produced on a 0.18-micron, six-layer process using a combination of aluminum and copper interconnect technology. The family uses copper in the top two layers of metal to reduce internal power supply voltage drop and minimize clock skew.

Virtex-E Extended Memory Family

Samples of the XCV812E(TM) are available now, and the XCV405E(TM) will be sampled in June. Both devices are expected to be in full production in third quarter this year. The XCV812E and the XCV405E devices are priced at $235 and $101, respectively for 50,000 units in Q4 2001.

     Device   Logic Cells  Dual-Port Block  Maximum Usable I/O
     ---------------------------------------------------------
     XCV405E    10,800          560K              404
     XCV812E    21,168          1120              556


Fully Supported Product Offering

In the Xilinx tradition of having cores available at the time of silicon availability, the Virtex-EM family is supported with the latest release of cores www.xilinx.com/ipcenter/coregen/updates.htm currently available and downloadable from the IP center (www.xilinx.com/ipcenter/index.htm). All the cores can be installed for use via the Xilinx COREGenerator(TM) System.

This cores release includes many Smart IP(TM) cores that are parameterizable, optimized, and predictable. For example, the release includes parameterizable generators for asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end.  FIFOs, block memory modules, distributed memory, parallel multipliers, FIR filters, FFTs, NCOs, Sine/Cosine LUT (LookUp Table) An array or matrix of values that contains data that is searched. See index and color palette. , and many more base level functions, as well as the configurable Reed Solomon Encoder and Decoder cores.

The current Xilinx Alliance Series(TM) and Foundation Series(TM) software version 2.1i fully support the XCV812E device. Software support for the XCV405E device will be available in the second quarter. For customers with a chosen EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  design flow, the Xilinx AllianceEDA program insures that industry-leading EDA vendors have tight integration with both the Alliance Series and Foundation Series software. As a result, the customer has a wide selection of EDA tools from which to choose, from design entry through simulation to board level verification.

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support.

Founded in 1984 and headquartered in San Jose, Xilinx invented the field programmable gate array See FPGA.  (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military and consumer markets.

For more information, visit the Xilinx web site at www.xilinx.com.
COPYRIGHT 2000 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2000, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:1USA
Date:Mar 27, 2000
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