Xilinx Alliance Series Software Supports Industry's First Ten Million Gate FPGA Designs.Business Editors/High-Tech Writers
SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--May 8, 2000
Xilinx eliminates deep sub-micron design gap through
silicon and software advancements
Xilinx Inc., (NASDAQ NASDAQ
in full National Association of Securities Dealers Automated Quotations
U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :XLNX) today announced its latest release of the Alliance Series(TM) software, version 3.1i. Designed for the future sub micron era of ten million gates, the new software incorporates the latest design flow enhancements with support for current Xilinx(R) architectures and future FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. architectures implemented with 0.15 micron and below. With the new capabilities of version 3.1i, systems designers will be able to implement multi-million gate designs without being plagued by many of the deep-submicron problems inherent in ASICs.
For example, the feature-rich Alliance Series software combined with advanced FPGA architectures shelters designers from parasitic issues such as crosstalk and ground bounce In electronic engineering, ground bounce is a phenomenon associated with transistor switching where the gate voltage can appear to be less than the local ground potential, causing the unstable operation of a logic gate. . The Alliance Series version 3.1i design flow enhancements include modular design In the context of systems engineering, modular design — or "modularity in design" — is an approach aiming to subdivide a system into smaller parts (modules) that can be independently created and then used in different systems to drive multiple functionalities. for teams of engineers working together, dramatic runtime improvements for timing closure, incremental design flows, and hierarchical floorplanning for designs of up to ten million gates. All of these capabilities further enhance the time-to-market advantages of programmable logic technology.
Demonstrations of all software products with the new version 3.1i software will be conducted at the Design Automation Conference in Xilinx booth no. 3629.
"As enhanced, high speed, high density Virtex(TM)-E FPGAs continue to replace ASICs, our leadership position in design software technology is playing a dominant role in this paradigm shift A dramatic change in methodology or practice. It often refers to a major change in thinking and planning, which ultimately changes the way projects are implemented. For example, accessing applications and data from the Web instead of from local servers is a paradigm shift. See paradigm. ," said Rich Sevcik, Xilinx senior vice president of IP, services, and software. "Our solutions enable designers to deliver increased product innovation and productivity through an integrated design flow that address many of the issues they previously faced while designing ASICs".
Xilinx modular design for design team collaboration
The Xilinx modular design tool in the new software version divides a design into functional modules in which a team member is assigned to each module. It allows full autonomy among team members to independently design, assign timing constraints, synthesize, and implement each module. Throughout the design cycle the modules can be placed in the design at any time, resulting in faster place and route run times and shorter time to timing closure for large designs.
4X runtime reduction for increase turns per day
Alliance Series software version 3.1i delivers algorithmic improvements in both timing analysis and place-and-route that dramatically reduce runtimes while delivering increased timing performance through first pass results. These advancements have up to a four-fold runtime reduction on large Virtex designs (greater than one million gates) and an average two-fold runtime reduction on smaller devices. These algorithmic advancements also deliver performance improvements of up to 15 percent on existing Virtex architectures.
Incremental design flows through synthesis partnerships
The Alliance Series 3.1i software provides guided place and route integrated together with synthesis tools from Synopsys Inc., Exemplar and Synplicity. This guide capability allows a designer to make small changes in their design without disturbing other unchanged portions of the design. This capability is mandatory in multi-million gate designs during the verification, debugging process.
Hierarchical floorplanning with graphic results
Xilinx has enhanced its robust floorplanner delivered in the version 3.1i release. The designer can resize Verb 1. resize - change the size of; make the size more appropriate
size - make to a size; bring to a suitable size
rescale - establish on a new scale area groups without deleting or reapplying logic, graphically assign I/Os to actual device pin locations, and manipulate the groups at hierarchical levels simplifying floorplanning for the synthesis process. These higher level functions aid in integration with modular design methodologies and Register Transfer Level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) level floorplanners. Within the Xilinx floorplanner a color-coded congestion The condition of a network when there is not enough bandwidth to support the current traffic load.
congestion - When the offered load of a data communication path exceeds the capacity. viewer allows the designer to avoid potential problems and intelligently allocate resources.
Price, platform, and availability
The Alliance Series software provides architecture-specific device support for all Xilinx product families, including Spartan(TM)/XL, Spartan-II, Virtex(TM), Virtex-E, Virtex-EM, and XC4000X(TM) FPGAs, plus XC9500(TM) and CoolRunner(R) CPLDs. The Alliance Series software is compatible for popular PC and workstation platforms and operating systems such as Windows95/98/2000 and Windows NT. Chinese, Korean, and Japanese Windows; Solaris and HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations.
(operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. . The new software version pricing starts at $1,495.
About Alliance Series software
The Alliance Series software is designed for companies who have made an investment in an EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. environment customized to suit the needs of their design engineers. The Xilinx Alliance Series software plug and plays by leveraging open systems standards, interfaces and formats such as EDIF EDIF - Electronic Design Interchange Format.
Not a programming language, but a format to simplify data transfer between CAD/CAE systems. LISP-like syntax. See also Berkeley EDIF200.
E-mail: <firstname.lastname@example.org> ftp://edif.cs.man.ac.uk/pub/edif. , SDF (Standard Data Format) A simple file format that uses fixed length fields. It is commonly used to transfer data between different programs.
SDF Pat Smith 5 E. 12 St. Rye NY Bob Jones 200 W. Main St. Palo Alto CA Comma delimited "Pat Smith","5 E. , VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , VITAL/Verilog and STAMP. Combining the strengths of our EDA partner tools with the advanced implementation features found in the Xilinx Alliance Series Software provides digital designers the ultimate in flexibility and design performance.
For customers with a chosen EDA design flow, the Xilinx AllianceEDA Program insures that industry leading EDA vendors have tight integration with the Alliance Series software. As a result, the customer has a wide selection of EDA tools from which to choose, from design entry through simulation to board level verification.
Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array See FPGA. (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.