XaQti Adds TrueSTATS RMON Processing and GMII Support to XMAC II Gigabit Ethernet Chip.

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 23, 1998--

GMII Offers Media Independent Interface; Gigabit Ethernet Speeds

Call For New Chip Architecture to Support RMON Management

XaQti Corporation, the Network-on-a-CHIP(TM) company, today announced the release of an enhanced version of its XMAC II Gigabit Ethernet Media Access Controller (MAC). The XMAC II, Rev C chip includes a full implementation of XaQti's TrueSTATS(TM), the only reliable chip counter implementation to collect gigabit and Remote Monitoring (RMON) statistics. The chip also includes Gigabit Media Independent Interface (GMII) support to deliver gigabit speed networking over 1000BASE-T unshielded twisted-pair cabling. This release makes XaQti the only merchant chipmaker currently shipping Gigabit Ethernet chips that integrate both RMON and support for the GMII.

The XMAC II chip architecture provides extensive traffic and event statistics using XaQti's TrueSTATS SNMP and RMON management counters. TrueSTATS' Snapshot Registers provides accurate traffic measurement on a fully loaded gigabit network without affecting performance or increasing the cost per port. This makes it easier for OEMs to address the growing demand for end-to-end network management for improved performance, proactive support and capacity planning. Integrating traffic and error statistics gathering in the networking chip allows information to be collected at the port level, without incurring the incremental costs and potential bottleneck problems of external embedded management CPUs. The chip without any host load constantly computes network utilization. The XaQti chip architecture is fully scaleable, so as the number of Gigabit Ethernet ports increase, the management cost-per-port increases proportionately rather than exponentially.

The dual-mode XMAC II media interface design allows OEMs to design Gigabit Ethernet products with interchangeable twisted-pair or fiber-optic media options. The XMAC II chip now supports both the 8B10B PCS fiber optic and GMII 8-bit externally encoded transceiver interfaces.

"As wire speeds increase, the shortcuts used in first and second-generation Ethernet chip designs no longer work," said Samba Murthy, Vice President of Marketing and Business Development for XaQti. "At gigabit speeds, maintaining traffic and network statistics is like trying to drink from a firehose. Rather than trying to retrofit 'tired' 10Mbps or 100Mbps chip designs to handle gigabit speeds, we have designed a gigabit network processing chip architecture from the ground up, incorporating statistics gathering with our unique TrueSTATS counter design. In addition, providing the GMII on all of our production Gigabit Ethernet chips will facilitate the early prototyping, testing and introduction of 1000BASE-T devices."

The Challenge of Gigabit and RMON Statistics

Gigabit data rates and enterprise network designs deliver performance and connectivity but can also propagate errors faster and more extensively. Because the amount of data required for RMON monitoring of gigabit networks grows exponentially as does the cost of hardware to process the data, "siliconizing" statistics collection is the only effective way to bring traffic and RMON management to gigabit networks.

For example, an 8-bit wide counter for the number of frames received will rollover, or 'wrap' (like a car odometer at 99,999 miles) more than 5,000 times a second at gigabit wire speeds (1.488 million frames per second) and a 16-bit counter will 'wrap' every second. With the XMAC II's 32-bit Received Frame counter, the system can automatically collect 24 hours of accurate traffic information and the Bytes Received/Bytes Transmitted counters are 64-bit counters for additional depth.

In order to gather accurate and useable traffic data for effective RMON processing, it is necessary to access accumulated traffic and error statistics on a real-time basis. There are three primary issues: -0-

1. The set of statistics for a switch port or backbone uplink

port should be "atomic," i.e. the value of each of the

statistical elements (collisions, long frames, frames

received, etc.) should correspond to the same instant in

time.

2. Packet counters should minimize overall system load and thus

per-port cost. With 10Mbps Ethernet, packets flow through

the chip at a maximum rate of 14,880 pps, a rate that allows

packets to be counted at the system level with an

inexpensive embedded processors if the chip does not provide

the needed on-chip error and traffic statistics. At gigabit

speeds, the packet rate jumps to 1.5 million pps - a rate

that is much too fast for any meaningful statistics to be

computed by an inexpensive embedded processor, particularly

since useful statistics, like network utilization, require a

number of compute cycles.

3. The statistics function must minimize data loss and

potential counter overflow and overrun. If on-chip counters

are 'shallow,' as in a typical implementation where the host

processing cycles are shared with other tasks, even one

thousandth of a second (one millisecond) of interrupted RMON

processing means valuable data is lost, and packet counters

can wrap once or many times. Large memory structures mapped

into multiple 'pseudo-registers' can fail to keep up as the

refresh cycle for read then write-back processing exceeds

the worst-case statistical update period.

To address these challenges, XaQti's TrueSTATS Snapshot Registers design ensures atomic and accurate statistics even in the midst of full burst network activity, eliminating the inherent access latency problems of other MAC counters. The XMAC II's internal counters can be copied to the Snapshot Registers at any moment. Because the counters are copied as a set, the transfer is instantaneous and the set of statistics is 'atomic' and will remain intact until the network management agent accesses all of the necessary information. This eliminates the potential for interleaved and non-atomic statistics and allows the use of slower, more cost-effective embedded processors. Transmit and Receive Utilization Statistics are constantly computed on-chip and instantly available.

The XMAC II's set of Etherstat MIB and gigabit-specific statistics conform to IEEE and ISO specifications and are all 32-bits wide to eliminate frequent counter 'wrapping'. To reduce system load and to ensure the correct processing of the largest statistics, TrueSTATS counters will automatically generate a maskable interrupt that signals every counter wrap. Using this interrupt, the system always knows where the packet "odometer" is set, whether the interrupt is at 100,000 packets or 500,000 packets, so the system does not need to manage timer values.

Finally, all of the TrueSTATS information is accessible through a 32-bit wide counter interface for faster access in transmit and receive modes. Traditionally, as 10Mbps and 100Mbps silicon engines try to ramp to higher packet rates, the 8-bit or 16-bit interface has created a bottleneck for network management data gathering. With the industry's first 32-bit interface, TrueSTATS has the bandwidth to facilitate statistics gathering at gigabit rates.

GMII Means Twisted Pair Gigabit Ethernet

XaQti's Gigabit Ethernet architecture also includes GMII dual-mode media support making the chip media independent. With GMII, the XaQti chip architecture supports the emerging 1000Mbps twisted-pair technology that will eventually become the 1000BASE-T specification. In addition to GMII, the XMAC II has always supported the 8B10B PCS-encoded fiber optic Gigabit Ethernet transceiver interface.

The media interface (defined as AUI for 10Mbps Ethernet and as the MII with Fast Ethernet) has evolved with Ethernet data rates. At 10Mbps speeds, data is received at the media interface as a Manchester encoded serial bitstream. With the 100 Mbps Fast Ethernet standard the receive and transmit data paths were broadened to a 4-bit wide interface. Gigabit Ethernet has further expanded the data paths to an 8-bit wide synchronous interface.

XaQti's chip architecture is designed to support both Fiber Channel and 1000BASE-T encoding schemes, giving manufacturers optimal design flexibility with the same chip set. In addition, XaQti's Gigabit Ethernet chip set is currently the only chip set to support both half-and full-duplex modes of operation.

Price and Availability

XaQti is currently sampling the XMAC II Gigabit Ethernet Media Access Controller (MAC) chip; the industry's first MAC chip to fully meet the new IEEE 802.3z D4 draft specifications for Gigabit Ethernet. The XMAC II chip is available in a 240-pin PQFP package and is priced at $45 in 10,000 piece quantities. Sampling quantities are available immediately and production quantities are expected to be available in June 1998, in conjunction with the anticipated ratification of the Gigabit Ethernet standard.

About XaQti Corporation

Founded in September 1995, XaQti Corporation is a privately held semiconductor supplier focused on advanced network and Gigabit Ethernet silicon solutions. The company's "Network on a Chip"(TM) vision enables innovative, scalable network processing solutions. The company's GigaPOWER(TM) protocol acceleration technology provides programmable 7-Layer Switching(TM) chips that enable traffic management by application for IP-switching, flow switching, multicast real-time video streaming, gigabit routing, VLAN, TrueSTATS(TM), RMON and SNMP network management.

XaQti Corporation is located 1630 Oakland Road, Building A214, San Jose, CA 95131; [phone]; FAX [phone], http://www.xaqti.com -0-

Note to Editors: XaQti, XMAC II, 7-Layer Switching, TrueSTATS, GigaPOWER, SuperMAC, uRMON and Network-on-a-CHIP are trademarks of XaQti Corporation. All other trademarks, service marks and registered trademarks mentioned in this document are the property of their respective owners.

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