World Leader In Yield Enhancement, PDF Solutions(R), Introduces New Release Of Circuit Surfer(R) For Optimizing Parametric Yield Of Analog/RF Chip Designs.

Circuit Surfer Helps Designers to Improve IC Performance and Yield, Speeding Time-to-Market and Profitability of Analog and Radio Frequency Chips

SAN JOSE, Calif. -- PDF Solutions([R]), Inc. (NASDAQ: PDFS) introduced a new release of its Circuit Surfer([R]) software for characterizing and optimizing the parametric yield of analog and radio frequency (RF) integrated circuit (IC) designs. The new release features the company's patented mismatch simulation technology, which helps to minimize the number of simulations required to characterize parametric yield. It also reduces design re-spins by identifying parametric yield loss mechanisms not visible when using verification methods based on corner modeling. Fabless semiconductor companies and integrated device manufacturers developing custom IC designs use Circuit Surfer where parametric performance and yield are crucial Co typically those containing analog/RF or other high-speed custom intellectual property (IP). PDF Solutions helps the world's semiconductor companies increase the manufacturability and yield of ICs at advanced process nodes.

"Parametric yield loss is driven by inter-die and intra-die (mismatch) parametric process variation," said Kevin MacLean, vice-president of marketing and development at PDF Solutions. "EDA tools today cannot efficiently and accurately verify or optimize parametric performance and yield in analog/RF custom IC design flows, nor can they give designers the critical parameters required for rapid design closure. With Circuit Surfer added to the design flow, chip yield can be optimized at the most advanced technology nodes, and at older nodes where ICs are being designed to push the performance limits of the process."

The Importance of Parametric Yield Enhancement in Analog and RF Chip Design

Device mismatch is the dominant form of parametric yield loss today in much of the custom IP used in ICs. From an IC schematic and layout perspective, designers typically are aware of which devices should be matched, but it is often unclear how much each of the matched sets of devices will affect circuit output variability. This is especially true for larger circuits with many matched sets of devices. Other than through direct current (DC) analyses, existing electronic design automation (EDA) tools do not make apparent to designers how mismatch will affect alternating current (AC), transient, and RF performance. Therefore, reducing the effects of mismatch typically results in creating unnecessarily larger area devices, which inherently makes non-beneficial trade-offs in layout area, power, and other chip traits.

Most design-for-manufacturing (DFM) and design-for-yield (DFY) software tools for circuit simulation suffer from the well-known limitations of Monte Carlo-based analyses: the number of circuit simulations required to quantify yield and the trade-offs with respect to the device areas to optimize performance and manufacturability. The greater the number of simulations, the longer it takes to accurately quantify yield, thus affecting overall verification times, time-to-market, and time-to-profit. Circuit Surfer alleviates long design cycles by reducing the total number of circuit simulations Co by 10x to 100x Co needed to obtain an accurate analysis of a chip's predicted performance and parametric yield. The parametric analysis capabilities in Circuit Surfer quickly identify, verify, and quantify for designers all of the critical individual process and device sensitivities, as well as pairs of matched devices and their contributions to the output variability. This shows designers which devices to focus on for both performance and yield improvement.

Availability and Pricing

Circuit Surfer is available now. The software is integrated into the Cadence Analog Design Environment (with Agilent RFDE) and is compatible with the Synopsys Hspice software. For more information or to order Circuit Surfer, contact [e-mail] or the nearest PDF sales office.

About PDF Solutions

PDF Solutions, Inc. (NASDAQ: PDFS) is the leading provider of process-design integration technologies and services for manufacturing integrated circuits (ICs). PDF Solutions enables semiconductor companies to create IC designs that can be more easily manufactured using manufacturing processes that are more capable. By simulating deep sub-micron product and process interactions, the PDF solution offers clients reduced time to market, increased IC yield and performance, and enhanced product reliability and profitability. Headquartered in San Jose, Calif., PDF Solutions operates worldwide with additional offices in China, Europe, and Japan. For the company's latest news and information, visit http://www.pdf.com/.

PDF Solutions, the PDF Solutions logo, and Circuit Surfer are registered trademarks of PDF Solutions, Inc. All other trademarks are property of their respective owners.