What designers need to know about testing: higher edge rates and HDI are taking their toll on time-tested testing methods. Now vision and flying probe test are taking off, but is test always necessary?

Certain traditional testing methods have been used since the early days of the PCB. These include clamshell fixtures for bare-board testing to detect opens/shorts; manufacturing defect analyzer (MDA) and in-circuit test (ICT) for fault detection/fault isolation on the production line; and functional test using rack and stack hardware with a unit under test (UUT) interface adapter at the operational level. Due to high-speed layout, stackup restrictions, blind/buried vias, and many other limitations these methods are less effective at testing many of today's PCBs.

First, let's reflect on bare-board issues. With the advent of HDI, which was driven mainly because of the BGA, chip-scale package (CSP) and flip chip, the traditional clamshell lost much of its utility. If one looks at the structure of a fully populated 0.050" BGA for an FPGA, the number of balls may be over 1,700 (ASICs with over 2,000 balls are now manufactured). When a bare-board clamshell fixture is used to interface with a fully populated 0.050" BGA, it requires 400 nails/i[n.sup.2]. If it's 1 mm pitch, it requires 625 nails/i[n.sup.2]. Constructing this type of fixture necessitates a high-density "piano wire" nail configuration, which drives up the fixture cost and is difficult to calibrate. Also, depending on the total number of BGAs and balls, the electrical drive/monitor resources of the tester can be overwhelmed. Making matters worse, 1 mm BGA and CSPs with pitches between 0.020" and 0.030" (with ball sites of 0.010" or 0.015") require leaning-pin fixtures with a number of alignment plates. This is a bare-board test nightmare. (Don't even ask about the flip chip or the 0.005" balls and 0.010" pitch!) FIGURE 1 provides an overview of grids and densities of various pin structures. Universal and dedicated bare-board fixtures are shown in FIGURES 2 and 3, respectively.

[FIGURE 1, 2, 3 OMITTED]

Along with all of the above, other bare-board test complexities have surfaced; e.g., blind/buried vias and buried resistors and capacitors within the stackup layers. Two newer types of bare-board testers can help solve these problems: flying probe and vision test. Flying probes have up to eight simultaneous moving probes on the top and bottom, 16 total, to test for opens, shorts, and in some cases, high-voltage and dielectric breakdown. Using target fiducials for alignment accuracy on the PCB (a CAD layout requirement), the probes can hit targets of 0.005", though some flying probe manufacturers claim even smaller targets). A bare board can be accurately tested using a flying probe.

The obvious drawbacks to flying probes are the cost of a new tester and its speed (throughput). However, when the issue is density or small targets such as blind via pads, the flying probe can be a lifesaver for ensuring quality of test. Some flying probes perform time-domain reflectrometry (TDR) testing. In lieu of a TDR tester, the bare-board coupons can be tested for [Z.sub.o] and inductance/capacitance discontinuities. These probes have fidelity up to 10 GHz. A typical probe for high frequency is shown in FIGURE 4.

[FIGURE 4 OMITTED]

Vision test has been used to check layer-by-layer artwork against CAD data. With blind vias usually made by a C[O.sub.2] laser, a new defect is appearing: a via opening that is not totally formed. The vision machine--either two-dimensional x-ray, laser or automatic optical inspection (AOI)--looks for debris in the via hole. If FR-4 debris is left in the hole, the plating process is placed in jeopardy, which in turn can cause cracking or non-copper continuity.

The test strategy question is, does it make sense to perform bare-board test? Is there enough of a payback? I have seen boards with 34 layers, 65 638-ball BGAs and over 58,000 solder joints. So, if this board (which cost about $100,000) is not tested, what is the downside? If an inner layer short/open is found after reflow (and after population with a massive number of components), what does this cost?

I have also observed simple boards, 24 per panel, which cost pennies; even after placement and soldering the assembled PCB cost $1 or less. If one PCB per 1,000 is defective, is it more cost-effective to pay for test and the associated costs (i.e., tester, fixture, test development, recurring test, etc.) or to simply discard the defective PCB? You decide.

Now, let's focus on testing the populated PCB. Again, HDI, blind via pads' target size and the increasing number of total interfaces challenge conventional ICT/MDA bed-of-nails (BoN) testers. For higher-density PCBs, pad targets are smaller. In addition, in many cases the BoN's pin misses the target, causing false failures. A number of fixtures have been designed (i.e., optical alignment, simulation plates, wireless fixtures, and vernier alignment techniques) but at a high cost and with ensuing calibration difficulties. Also, 0.050" BGAs are driving the state-of-the-art of BoN fixtures, to the point of having two adjacent wire-wrap pins with a spacing of 0.050".

A standard rule for ICT is that every electrical node must be available on the bottom of the PCB. If this is achieved through the BoN, the tester will have access to all nodes and, to a high degree, the capability to detect and isolate a fault. More than 95% of faults consist of opens, shorts, backward components, wrong value components, and missing components. This is known as the classical fault spectrum created by the manufacturing line. Therefore, it is best to ensure that all signal nodes are via'd to the underside. Does this make sense for today's high-frequency, high switching-rate PCBs? Presently PCBs contain ICs with very fast switching rates. TTL and CMOS have switching edges less of than 1 nsec and ECL, SiGe, GaAr, and InPb switch down to 17 psec. (Note: IBM built a transistor that can be clocked at 150 GHz.).

The inductance (L) of vias is the problem. By empirical measurement, vias have ranged from 0.4 nH (blind) to 2 nH (backplane/motherboard) and this L can totally degrade signal integrity by causing ground bounce, crosstalk, EMI and decoupling between power and ground planes/structures. (For signal integrity gurus, it is the total loop L that is the determining factor, but for this discussion we are considering just the vias.) Let's look at an example.

The formula [X.sub.L] = 2[pi]fL provides the expression for inductive reactance, but here f is the knee frequency which is defined as 0.5/Tr, Tr = rise time. The faster the rise time, the more energy will exist in the high order harmonics that make up rising edge transition. So it's not the basic frequency (like a clock) but the harmonic content of the edge. Now, assume our edge is 1 nsec, and the PCB is a backplane. Therefore:

[X.sub.L] = 2[pi] (0.5)([10.sup.9])(2 x [10.sup.9]) = 6.28[ohm] (2 x [10.sup.9] = backplane via L)

This means that the via to the 1 nsec edge creates an impedance that will wreak havoc with ground bounce, bypassing and EMI. Many companies' design rules prohibit vias for strictly test purposes. Why not use clamshelling, as with bare boards (FIGURE 5). Using BoN fixturing for topside access has the following drawbacks:

[FIGURE 5 OMITTED]

* It is more costly.

* It is pneumatically actuated (versus vacuum for the underside) and the BON's pin "pointing vector error" (i.e., its possible tilt angle from straight up) is much greater. This requires much larger targets, which is totally contrary to the high-density concept. Also, in many cases it requires hitting IC pin pads versus via pads if the via pad is <0.040".

* Aligning and calibrating the topside is an issue. Considering this, the evolving testing concept is:

* Flying probe and vision test (as with bare boards).

* Intermediate testing on the line, such as using MDA with minimum BoN testing after chipshooting/pick-and-place but before odd-form components are placed. (Can you detect a defective, missing or wrong-value 100 pF ceramic in parallel with 10 [micro]F aluminum electrolytic/tantalum?)

* Vision testing after printing, checking for volume and position of critical solder brinks. After stencil printing, "value add" on the production line is a big concern. For example, what does it cost to remove and replace a 600-ball BGA if an inner ball has no solder because of a clogged stencil aperture opening? Also, vision testing after chipshooting. (Did the 0201s really get placed and how accurately?)

* Built-in test (BIT), such as JTAG (IEEE 1149.1) or other SCAN structures, and software BIT at the end of the line.

For SMT manufacturing engineers, the second and third bullets (above) may create bottlenecks for production runs. It boils down to a tradeoff between defect detection and throughput. Currently the end-of-the-line testing can consist of three distinct test methodologies:

1. Vision: Used mainly as a quality test (fillet size, joint quality, component skew, etc.), but also very useful for finding catastrophic faults such as backward parts (polarized capacitors and diodes) and wrong-value parts (such as SMT resistors of correct size but incorrect value).

2. Flying probe: Great for prototypes when the ICT BoN fixture is still being manufactured. Also, today all flying probes have vision and some incorporate JTAG. Single-side probes can hit targets of <0.005" and therefore can test flip-chip interconnects.

3. ICT: Used for the bulk of testing. Now have JTAG compatibility, and when using wireless fixtures (FIGURE 6) can test in the MHz range. Incidentally, the maximum L and C that a PCB ever sees is the wire-wrap loading in a BON's wire wrap fixture. Therefore, the wireless fixture can test to a much higher frequency.

[FIGURE 6 OMITTED]

ROBERT HANSON, MSEE, is president of AmeriCom Test and SMTTechnology Inc. As a digital design engineer at Boeing, Rockwell, Honeywell and Loral, Hanson designed and provided prototype operational analysis on many high-speed designs, including PCBs, for the AWACS, B1-B, 747-400, various missiles and ground support test equipment. He is scheduled to speak at PCB Design Conference East in October. Hanson can be reached at [e-mail].