Waferscale's Low-cost 68HC11 Development Kit Enables Quick Prototyping and Debugging of 68HC11 Systems.FREMONT, Calif.--(BUSINESS WIRE)--Oct. 18, 1999-- Waferscale Integration, Incorporated (WSI See wafer scale integration. ) today introduced a comprehensive prototyping and debugging environment for designers of 68HC11 MCU-based systems with external memory and logic provided by the company's EasyFLASH(TM) PSD (tool) PSD - Portable Scheme Debugger. 8XXF, PSD3XX and PSD211R MCU (1) (MicroController Unit) A computer on a single chip. See microcontroller. (2) (Multipoint Control Unit) A device that is used to moderate a videoconference of three or more end points (users at computers or groups of users support ICs. The EasyFLASH-68HC11(TM) development environment accelerates system development by allowing designers to quickly prototype and debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. complete embedded systems Embedded systems Computer systems that cannot be programmed by the user because they are preprogrammed for a specific task and are buried within the equipment they serve. designs, including the MCU code, the PSD's external logic and memory, external peripherals, memory mapping Memory mapping is a process whereby some item of digital hardware is connected to a processor's address bus and data bus in such a way that it can be accessed (for reading and/or writing) exactly as if it were a memory cell. , and ISP (1) See in-system programmable. (2) (Internet Service Provider) An organization that provides access to the Internet. Connection to the user is provided via dial-up, ISDN, cable, DSL and T1/T3 lines. capabilities. The only other way to prototype 68HC11 designs with external peripherals is to build a printed circuit board. According to according to prep. 1. As stated or indicated by; on the authority of: according to historians. 2. In keeping with: according to instructions. 3. David Raun, Waferscale's vice president of marketing, "More and more product features are being implemented in software. This approach provides flexibility and speeds up development cycles. It also rapidly expands the amount of required program storage beyond the capabilities of most single-chip microcontrollers. Other factors are also contributing to a phenomenal growth in flash memory requirements of embedded systems. Designers are using large lookup tables to store the pre-calculated values of complex control algorithms and they are designing systems that store large amounts of data over long periods. It is common for these systems to require 128 to 256 Kbytes or even more flash memory -- substantially more than is available on any Motorola microcontroller. This combined with the fact that the 68HC11 family does not offer any devices with flash memory creates a real challenge for many long time 68HC11 users. In these situations, the designer must add external flash, plus multiple chips for address decoding, latching, and extra I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output . These extra chips can double or triple the required board space and can increase power consumption by an order of magnitude A change in quantity or volume as measured by the decimal point. For example, from tens to hundreds is one order of magnitude. Tens to thousands is two orders of magnitude; tens to millions is three orders of magnitude, etc. . It also lengthens the development cycle and increases system costs," Raun explained. "Furthermore, until now, there has been no practical way to debug these designs. Although an ICE can be used to develop and debug the MCU code, the only way to see how the external logic and memory work with the firmware has been to build a custom printed circuit board -- a process that extends the development cycle by several weeks. "Waferscale's EasyFLASH-68HC11 development environment completely solves this problem by providing two printed circuit boards that include the core MCU, the PSD of the designer's choice, and an array of development tools. A design developed in this environment will have the exact same combination of flash, EEPROM (Electrically Erasable Programmable ROM) A rewritable memory chip that holds its content without power. Although EEPROMs spawned flash memory, EEPROMs are byte addressable at the write level, whereas flash chips must erase a block of bytes before rewriting. or EPROM EPROM in full erasable programmable read-only memory Form of computer memory that does not lose its content when the power supply is cut off and that can be erased and reused. , SRAM See static RAM. SRAM - static random-access memory , I/O, programmable logic and other external devices that the designer has selected for the final design. "As far as we know, Waferscale is the only vendor offering a development system that supports the use of external memory, logic and other external devices with Motorola's 68HC11 microcontrollers. With the EasyFLASH-68HC11 development kit and an appropriate PSD device, it is exceptionally easy to develop and debug 68HC11-based systems with our external memory and logic. Waferscale's PSDs are cost effective, low-power, single-chip devices that provide designers with various combinations of programmable logic, non-volatile memory, SRAM and I/O so they end up with a two-chip solution, avoiding the hassle associated with adding discrete external memory or logic. PSDs are designed to work with the 68HC11 architecture. They have a programmable interface that can be configured for the 68HC11 in just a few seconds. In-system programmable flash PSDs go a step further by solving the substantial problems associated with implementing in-system programming (ISP) with the 68HC11 architecture. The 68HC11 architecture will not allow writes to program memory space, making it extremely difficult to effect MCU-controlled ISP. A special ISP decoding PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. on PSD8XXF devices automatically handles address reclassification Reclassification The process of changing the class of mutual funds once certain requirements have been met. These requirements are generally placed on load mutual funds. Reclassification is not considered to be a taxable event. so the 68HC11 can perform erase/writes to the flash memory. The PSD's on-chip CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. is directly connected to the MCU address/data bus, eliminating the need to build an interface between the CPLD flip flops and the MCU and conserving product terms for the implementation of system logic. EasyFLASH-68HC11 Development Kit Configuration. The EasyFLASH-68HC11 development kit consists of an MCU mother board (68HC11 MCU included), a PSD daughter board (PSD813F1 included), a Cosmic CX68C11 compiler, Waferscale's PSDsoft(TM) 5.0 EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. software, and Waferscale's FlashLINK(TM) Programmer for in-system programming via the PSD's JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group interface. MCU Mother Board. The EasyFLASH-68HC11 mother board includes an 68HC11 MCU with two timer/counters and 128 bytes of RAM; an 8-bit asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end. UART (Universal Asynchronous Receiver Transmitter) The electronic circuit that makes up the serial port. Also known as "universal serial asynchronous receiver transmitter" (USART), it converts parallel bytes from the CPU into serial bits for transmission, and vice ; a 9-pin RS232 interface; a four position dip switch to set the execution code source (flash, EEPROM or SRAM); a debug RAM for break point capability; a 2.4 inch by 2.5 inch prototype area that is connected to the MCU's address/data bus and control signals; expansion slots to expand the prototype area; a reset switch; and a 2 x 16 LCD display that echos serial commands during debug and annunciates the results of ongoing tests (e.g. page register, ok, RAM, ok, etc.). The prototype area can be used to add external devices that will be included in the system, such as a DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter or ADC (1) See A/D converter. (2) (Apple Display Connector) A peripheral connector from Apple that combines digital video display, USB and power in one cable. . The expansion slots allow the addition of additional prototype boards. The EasyFLASH-68HC11 mother board provides three power supply options: a holder for a 9-Volt battery for prototyping portable applications, a standard transformer, or an external power supply to allow JTAG chaining or to accommodate user expansion. A Choice of PSD Daughter Boards - The EasyFLASH-68HC11 Development Kit includes a PSD813F daughter board populated with a 100% in-system programmable PSD813F1. Any of the ten available flash PSD8XXF derivatives can be plugged into the daughter board socket to exactly represent the configuration of the design. A second, optional daughter board is available that supports Waferscale's PSD3XX and PSD211R devices. All daughter boards provide a jumper (JP1) to measure PSD current consumption. Current consumption is measured by placing a resistor in series with the PSD and then measuring the voltage drop across the resistor. JTAG connectors on the PSD813F daughter board provide access to the PSD813F's JTAG interface for JTAG programming of the PLD, MCU interface configuration, flash and boot memories. During ISP, JTAG traffic can be observed via LEDs mounted on the daughter board. PSDsoft(TM) 5.0 EDA Tool Suite - PSDsoft 5.0 supports HDL-based logic design of the 3,000 gate on-chip CPLD, using MINC's AHDL AHDL - Analog Hardware Design Language . MCU interface configuration, I/O control, memory mapping, and the configuration of programmable functions are handled quickly using radio buttons on pull-down menus and dialog boxes. PSDsoft automatically generates C-routines for the implementation of MCU-controlled in-system-programmability and ensures there is no conflict between the addresses assigned to the logic and microcontroller firmware. Without PSDsoft, designers must manually verify there is no address overlap, a difficult and time-consuming process. PSDsoft 5.0 runs under Windows(R) 95/98/NT. Cosmic CX6811 C Cross Compiler - Cosmic Software's third-party C Compiler package includes an optimizing ANSI-C cross compiler, macro assembler, linker, librarian, hex file generator, object format converters, debugging support utilities, run-time library source code, and a multi-pass compiler command driver. A special code generator and optimizer targeted for the 68HC11 family eliminates the overhead and complexity associated with generic compilers. In addition, header files for many 68HC11 peripherals allow the designer to access memory mapped objects by name either at the C or at the assembly language levels. Runtime library functions include: character handling, mathematical functions, non-local jumps, formatted serial input/output, string handling and memory management. FlashLINK ISP Programmer - Waferscale's FlashLINK programmer allows designers to quickly perform first-time and subsequent in-system programming of PSD8XXF devices (via a JTAG interface), either in the EasyFLASH-68HC11 development environment or in the target system. The compact FlashLINK programmer connects to the parallel port of a PC or notebook computer. Test Routines Included - Waferscale provides several software routines to test the development board hardware, for code copy tests, and to test the UART. The code copy test is used to test the ISP memory swapping capabilities of the PSD813F device. This is important because 68HC11 microcontrollers cannot write to program space, so memory swapping must be implemented in order to effect MCU-controlled ISP. Price and Availability - Waferscale's EasyFLASH-68HC11 development kit is available now and costs $399 total for the mother board with 68HC11 MCU, daughter board with PSD813F1, PSDsoft 5.0 EDA tools, Cosmic CX6811 compiler, and Waferscale's FlashLINK programmer. A second optional daughter board for use with PSD3XX and PSD211R devices is available for an additional $65. Waferscale's World Wide Web site is www.waferscale.com. Waferscale Integration, Incorporated is the leading supplier of highly integrated programmable solutions for cost sensitive embedded control designs. Its PSD families of single-chip, field-programmable microcontroller peripherals off-load microcontroller functions so that MCUs can operate faster and do more. The power-conserving features of PSD devices can extend system battery life by several hours. The company's family of high performance non-volatile memory products offers densities of 16 Kbit to 1 Megabit with access times as low as 25 ns and 3.3 volt devices with access times as low as 70 ns. Waferscale is located in Fremont, California. EasyFLASH-68HC11, PSDsoft, EasyFLASH and FlashLINK are trademarks of Waferscale. Windows is a registered trademark of Microsoft Corporation. |
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