Wafer-Level event to track IC packaging.

The first annual International Wafer-Level Packaging Congress (IWLPC) to explore semiconductor packaging and test technologies, with special emphasis on three-dimensional (3-D) stacked packaging, will be presented in San Jose, CA, on Oct. 10-12. The congress and exhibition are sponsored jointly by the Surface Mount Technology Association (SMTA, Minneapolis, MN, www.smta.org) and Chip Scale Review magazine (San Jose, CA, www.chipscalereview.com).

SMTA vice president of technical programs Dr. Ken Gilleo of ET-Trends LLC and Joseph Fjelstad, co-founder of SiliconPipe, will co-chair the technical program. Both are respected speakers on semiconductor packaging and interconnection topics. Session speakers will include Dr. Thomas Di Stefano, who is recognized as a pioneer in the development and adaptation of chip-scale and wafer-level packaging.

In addition to its focus on WLP, the congress will explore many topics in chip-scale packaging and other advanced packaging processes. A key area of interest scheduled for discussion is 3-D packaging. The dual-track program will address package design concerns, package assembly, fabrication technologies, board design for chip-scale packages and test/reliability. Featured workshops will explore issues in wire bonding, wafer bumping, encapsulants, lead-free strategies and test.

"Wafer-level packaging is a pivotal technology that should see an expanded role in integrated circuit (IC) packaging owing to the many potential benefits it offers IC product developers, including cost savings and increased performance," said Fjelstad.

"Although wafer-level packaging is crossing into the mainstream, other important technologies, such as 3-D packaging and wafer bonding, are becoming increasingly important to the semiconductor industry," said Gilleo. "Congress attendees will learn how wafer-level packaging, chip-scale packaging, system-on-chip, system-on-package and other technologies will affect the semiconductor packaging business."