Virtuoso 4.2 IDE Has Multiprocessor DSP RTOS, Graphical Debugging Tools and World's Only Multitasking Network Host Server.

Business Editors and High Tech Writers

Embedded Systems Conference 2000

Booth 1817

SANTA CLARA, Calif.--(BUSINESS WIRE)--Sept. 26, 2000

Multithreaded Network Server Transfers Data from Host 50 Times Faster

Eonic Systems today unveiled its Virtuoso(TM) 4.2 Integrated Development Environment (IDE), for the design of multiprocessor embedded DSP networks, such a radar, sonar and high-end image processing. The Virtuoso 4.2 IDE includes the Virtuoso 4.2 RTOS, a project manager, a new multi-threaded asynchronous network host server, and a suite of graphical analysis and debugging tools, as well as plug-ins to TI's Code Composer Studio and ADI's Visual DSP. The newest version of the Virtuoso RTOS offers a variety of features that are not available with any other RTOS, a single processor programming style for multiprocessor systems, both communicating sequential processes (CSP)and multithreading multitasking capabilities, static memory allocation, target channels that allow data to be sent and received at different data rates without buffers, and distributed, shared or pooled memory architectures. The Virtuoso IDE supports Jovian's Pegasus graphical DSP development environment.

According to Jan Rosseel, Eonic's Director of Engineering, "Designers of high-end systems with multiple DSPs face several challenges. First DSP applications are data and computation intensive, processing billions of operations on multiple megabytes of data each second. They are interrupt intensive with thousands of interrupts a second. The processors themselves are architecturally very different from microcontrollers: They have extremely small on-chip memory, meaning that the code size must be kept at a minimum and time-critical operations or data must be kept in the fastest processor memory. They have multiple internal and external busses that support parallel processing and they have lots of interrupts. Conventional multithreading RTOSs simply don't have a feature set that supports these applications or architectures.

"Eonic has developed its Virtuoso IDE with RTOS specifically to handle the heavy interrupt and data processing demands of DSP applications and to exploit as fully as possible the DSP architecture -- particularly in applications with multiple processors. The Virtuoso RTOS also exploits the parallelism inherent in DSP architectures to achieve maximum hard real-time performance in the smallest possible amount of code.

"Virtuoso's scalability and portability allows designers to design on one processor today and then move to the next generation processor as soon as it is available, without any reprogramming. New processor architectures that do more processing faster are appearing on the market all the time. For example, two TMS320C6X DSPs can achieve the same throughput as six TMS320C4X DSPs. Many designers want to migrate their designs to the faster processors to achieve increased performance, on a smaller board with less power consumption. Using conventional multithreading techniques available in most general purpose RTOSs, changing architectures requires a new design, pretty much from scratch. Virtuoso offers a unique combination of multithreading and communicating sequential processor (CSP) multitasking techniques that allows designs to be completely scalable to more or fewer processors and makes designs 100% portable between different processor architectures, without changing the code. As far as we know, Virtuoso is the only RTOS that can boast this capability," Rosseel concluded.

Multithreaded, Asynchronous Network Server - Embedded networks such as industrial control systems, high speed inspections systems, radar and sonar frequently require a graphical interface to an operator. Although virtually all RTOSs offer some support for multiple processors, there has been no integrated solution that supports multitasking on the network host side. As a result only one application task may access the outside world at any time. For example, data may not be transferred from a TCP/IP or Ethernet network to the host at the same time that the keyboard is being used. The penalty for this situation is that data transfer rates between the systems processors and the network host server are severely restricted - usually to no more than a few hundred kilobytes per second.

Virtuoso 4.2 is the first RTOS ever to implement asynchronous multitasking on the network server. Virtuoso uses a communicating sequential process (CSP) multitasking model that allows direct communication between any target task and any network host server-based application. One side of the communication can be a Virtuoso target task that communicates using a channel, while the other side of the communication can be a host-based application that communicates using a file, a named pipe, a COM port or a TCP/IP socket. Network host server multitasking speeds up data transfers by several orders of magnitude. Virtuoso 4.2 has achieved data transfer rates between the network host server and application processors of 16 megabytes per second (MB/s) -- over 50 times faster than using a conventional, non-multitasking host/target communications protocol.

RTOS Achieves 100% Scalability By Combining CSP and Multithreading - Most real-time operating systems, such as pSOS, VxWorks and Windows implement multitasking using threads. Each task has its own thread and all threads that must communicate with each other must share the same memory space. The threads are synchronized using semaphores (to signal when data is ready) and mutexes (to lock and unlock resources which are in use). In single processor systems that do not require "hard" real-time operation, multithreading can be very fast and efficient. However, as processors are added to the system, memory accesses by multiple processors creates a bottleneck on the bus that degrades performance. In a system with a 200 MHz processor, the addition of even a second processor may actually reduce overall system performance. Shared memory has another drawback in that the engineer must individually design sub-applications and manage the memory for each processor in the system. In short, a separate program must be written for each of the system processors. These systems are not easily scalable to more or fewer processors. Moving tasks between processors or to a new processor is extremely difficult and can result in erroneous pointers, premature overwriting of data, or memory fragmentation. Taking advantage of a new DSP architecture that can do the same job with fewer processors requires the designer to rewrite the application from scratch. Thus, even though the application is implemented almost entirely in software, it is still not very re-usable if the hardware changes.

Virtuoso 4.2 solves the multiprocessor bottleneck and the scalability problem by combining the communicating sequential processor (CSP) multitasking model and the multithreading model in the same RTOS. In the CSP model. tasks (similar to threads) communicate directly through channels that serve as data-flow pipes. The channels exploit the multiple external buses or the direct link ports available on DSPs, so the DSPs communicate directly with each other without using the system bus.

CSP Target Channels Eliminate the Need for Data Buffers - In Virtuoso 4.2 all processors have access to each other's memory (distributed memory) and each task has its own dedicated memory space. Virtuoso 4.2 also offers "pooled" memory, a variant of distributed memory that treats all system memory as a huge single block of memory, thereby preventing fragmentation and optimizing memory usage.

In CSP, data is copied directly from one task to another, via the channels using mailboxes. Synchronization services such as semaphores and mutexes, are not necessary with CSP. Special target channels in Virtuoso 4.2 allow arbitrarily different data transfer rates at opposite ends of the channel, without any buffering. For example, a driver task may be able to fetch only eight samples at a time from the I/O card, while the processor needs to process 256 samples at a time. Typically either the I/O driver task or the processor would have to buffer the data until enough was available for the processor. This situation requires buffering code and results in a dependency between the driver and processing tasks that reduces scalability by making it more difficult to move tasks between processors or to change to an I/O device with a faster data rate. Virtuoso 4.2's target channels allow the driver task to read and put small blocks of data in the channel, while allowing the processing task to read the larger blocks it needs for processing, without any special code or buffers. The target channels in the RTOS automatically handles the disparity in data rates.

Virtuoso 4.2 also offers the option of using the shared memory and synchronization resources usually associated with multithreading. Shared memory can be faster and use less memory than CSP channels and is particularly useful for exchanging parameters, sharing large data sets, and if the system has a relatively small number of processors. In fact, Virtuoso allows the designer to switch between the multithreaded and CSP multitasking models within the same task. Virtuoso 4.2 is the only RTOS on the market today that offers both multithreading and CSP options.

Virtual Single Processor Model - Virtuoso's CSP-based multitasking allows the designer to write code for a single processor system, but execute that code on any number of processors regardless of pointers, etc. Processors can be added to enhance performance or removed when a more powerful architecture becomes available without rewriting any code. The designer distributes the tasks over the various processors, or "nodes", by simply dragging and dropping them from within the Project Manager. Adding and removing processors is as simple as remapping the objects in the project file.

Drag and Drop DSP Design Using Jovian's Pegasus - Jovian's Pegasus graphical DSP design environment is seamlessly integrated with Virtuoso 4.2. Pegasus allows designers to create and simulate DSP designs by graphically dragging and dropping pre-defined blocks of functionality into a block diagram. Once the designer is satisfied with the simulation, Pegasus will automatically generate the required C-code. Its DSParCer separates the code into individual tasks and writes the DSP-specific code that can be run in parallel on one or more DSP processors. Pegasus also writes a makefile that runs the DSP compiler, linker and the Virtuoso RTOS configuration tools.

Static Memory Allocation Ensures Deterministic Response - "Hard" real-time means that tasks are executed within a precise time frame 100% of the time. In a multiprocessor system with thousands of interrupts a second, and multiple levels of prioritization, achieving hard real-time performance can be difficult. Virtually all high end DSPs have internal cache memory that stores the most recently executed instructions and external memory is added for code and data storage. Most RTOSs treat all the memory as a giant "heap" in which all data, stacks, and code are stored. Although instructions in cache can be executed very quickly, there is never enough cache to store all the code, with the result that required code is only available from cache memory 70% to 80% of the time. When time-critical code is not cached, performance is degraded. More importantly, the non-deterministic nature of cached memory is entirely unacceptable in hard real-time systems. Virtuoso solves this problem by allowing each segment of the system memory to be statically assigned by the designer. This ensures that the stack of tasks that must be handled quickly, such as driver tasks and interrupt service routines, are kept in internal memory and tasks that are not in the critical path, such as background control tasks, are stored in slower and cheaper external memory. Virtuoso checks the memory allocation to ensure that the heaps are the correct size.

Comprehensive Scheduling Options - Virtuoso 4.2 provides a wide range of scheduling options including: round robin with prioritization, time-slicing, prioritized and preemptive scheduling. Virtuoso also supports priority "inheritance" to protect tasks from being blocked during resource sharing.

Multi-level Microkernel Architecture Minimizes Kernel Size - Virtuoso 4.2 has two interrupt handling levels that can disable or enable global interrupts and are capable of processing an interrupt service request (ISR) in less than one microsecond, a "nanokernel" that uses prioritized round-robin scheduling to manage system-level tasks with context switch times as fast as 500 ns (50 MHz, ADSP-21060), and a microkernel that manages C-language application-level tasks that are defined by the designer. Each task has its own processor context, priority, stack, and predefined entry point and all tasks are fully prioritizable and preemptive. The Virtuoso microkernel provides over 90 kernel services that include task, memory, resource and timer management; as well as queue, mailbox, semaphore and event services. Microkernel task code is completely portable and scalable, and can be ported to other processors.

Virtuoso 4.2's unique architecture minimizes the number of registers used, speeds up context switching, and prevents interrupts from disabling the system so processor performance is maximized. During runtime application generation, Virtuoso 4.2's SoftStealth(TM) technology automatically eliminates any excess code, minimizing the memory footprint of the OS kernel to between 2K to 15K instructions and guaranteeing optimum performance.

Graphic Analysis and Debugging Tools For System Optimization - Virtuoso is the world's only IDE that provides a graphical design analysis and debugging capability for DSP-based systems. Virtuoso 4.2's real-time tracing monitor allows the user to analyze in detail all system events with clock cycle precision in an interactive graphical format. For any node, the real-time tracing monitor graphically displays the scheduling of the tasks on the node. Clicking on any point on the time trace launches a status window that shows the precise details at that time (tracer entry number, node ID, active task, event system name, timer value, relative time required, kernel services in use and event description). By examining the pattern of task execution, the designer can determine if the scheduling is right or wrong. For example, if the idle task is active for too long, resources are being wasted and more tasks should be assigned to that processor at that time. A single processor or a whole network of processors, can be navigated with just the click of a mouse. The information is displayed in separate windows for each node. Virtuoso 4.2 also includes a graphical real-time task-level debugger.

Processors and Boards Supported - Virtuoso supports high performance processor cores, discrete DSPs and high-end microprocessors from Analog Devices (ADSP-21020, ADSP-2106x and ADSP-21160 SHARC DSP Families), Texas Instruments (TSM320C3X, 320C4X, 320C54X, 320C62XX, 320C64XX and 320C67XX), Advanced RISC Machines (ARM, ARM7T, and ARM9), IBM/Motorola (PowerPC G3 & G4 Altivec) and Infineon's Carmel.

Virtuoso can be used to design multi-processor systems using Analog Devices' ADSP-2120, 2106X and 2116x, and Texas Instruments' TSM320C4X, 320C62XX, and 320C67XX.

Virtuoso 4.2 supports virtually all customer-off-the-shelf (COTS) boards. Eonic has developed its own high availability Atlas CompactPCI boards and the complete Atlas Universal Digital Signal Computer specifically to support the advanced features in the Virtuoso RTOS. Using the Atlas computer and Virtuoso, designers can develop their software before or during hardware selection. Designs will be 100% portable between processor architectures and scalable to more or fewer processors.

Support For Third Party Tools -Virtuoso offers seamless integration with third party debugging tools, compilers, source-level debuggers, and IDEs. Products currently supported include Texas Instruments' Code Composer Studio. Product support is currently in development for Allant Software Corporation's ASPEX(R) and Analog Devices' Visual DSP(R) software development tools. With TI's Code Composer, use can be made of the RTDX mechanism to establish a host to target communication over the standard JTAG emulator cable.

Price and Availability - Virtuoso 4.2 is available now and is priced at $10K for single processor targets and $20K for Virtual Single Processor support for multiprocessor systems. Special pricing is available for universities, COTS board vendors and high volume corporate users.

Eonic Systems was founded in 1989 to develop high performance programming tools for hard or soft real-time embedded applications using high performance DSP, microprocessor and ASIC cores. The company's Virtuoso embedded systems development environment provides a four-layer, prioritized preemptive real-time operating system that fits in as little as 2K words of memory and can provide context switching as fast as 200 ns. Virtuoso's Virtual Single Processor designs are 100% portable and scalable and can be implemented on one or multiple processors or ported to different processor architectures without affecting the C-language application code.

Eonic Systems is a member of various Partner Programs including Analog Devices' DSP Collaborative(TM), Texas Instruments' Third Party Network and Infineon's Carmel DSP Alliance.

Atlas, Eonic, SoftStealth and Virtuoso are trademarks of Eonic Systems. All other trademarks are property of their respective holders.