Viewlogic offers unique deep sub-micron test capability; Sunrise TestGen takes design to .18 micron.

MARLBORO, Mass.--(BUSINESS WIRE)--May 8, 1997--Targeting the test challenges posed by .18 micron geometry silicon, Viewlogic Systems, Inc. (NASDAQ: VIEW) today announced a broad attack on deep sub-micron test issues with several new tools for the Sunrise TestGen tool suite. To move beyond stuck-at faults, the Sunrise PathTest delay test generation tool uses Viewlogic's MOTIVE static timing analysis tool to target timing-related defects that are more prevalent at small geometries. Another new tool, ScanPlanner, considers physical placement information during test synthesis. The new Parallel FaultSim tool increases fault simulation throughput for the support of system-level ICs with over one million gates. Also included are feature enhancements in SHERLOC to address silicon debug requirements for complex deep sub-micron ICs.

"The test challenges posed by deep sub-micron design are significant," explained Mark Milligan, Vice President of Viewlogic's Sunrise Test Unit. "The stuck-at fault model that the industry has relied on for 30 years is no longer sufficient. The close proximity of wires makes bridging faults very likely and the high clock rates possible with the latest silicon technology make it imperative to test for timing-related manufacturing defects."

The new TestGen tool suite generates tests for bridging faults that occur between neighboring wires. To identify defects that could allow a chip to test correctly on the tester, but fail in the system when running at full clock speed, the tools build a bridge between the industry's most popular static timing analysis tool, Viewlogic's MOTIVE and the PathTest path delay testing capability. Static timing analysis identifies the possible critical paths in a design, without the use of test patterns. To test these same paths on the tester and ensure that they function at speed, the TestGen tool suite imports those critical paths from MOTIVE and creates manufacturing tests for them using PathTest.

Another challenge in deep sub-micron design is bringing physical placement information into test synthesis. Advanced design for test (DFT) methodologies typically rely on insertion of additional electronic circuitry to improve the testability of the device. Traditional test synthesis tools, however, have no knowledge of the eventual physical placement and routing of the test circuitry. Consequently, insertion of test structures can use as much as 15-20% of the silicon die area. The new ScanPlanner tool minimizes the silicon overhead of DFT methodologies by driving popular place and route tools. ScanPlanner orders scan path elements based on physical placement data. It's knowledge of the circuit clock origins and polarities eliminates skew and timing hazards. The place and route tools provide feedback to ScanPlanner to generate an updated circuit database and to format test vectors prior to manufacturing release. The automatic test pattern generation (ATPG) process does not need to be rerun. ScanPlanner supports the Cadence GateEnsemble and CELL3 tools and Avant! AquariusBV and AquariusGA tools.

Sunrise TestGen also now includes, as a new option, Parallel FaultSim fault simulation capability to grade existing user-provided test vectors and to increase fault simulation throughput by distributing the process across a network of computer systems. Today's system level ICs contain millions of transistors and complex on-chip functions, such as MPEG decoders, 3-D graphics and high-speed networking engines. With the advent of system level ICs, one test method is not sufficient. Different techniques must be used to address the various design modules in these complex chips. Fault simulation of functional patterns, while largely replaced by scan design over the last few years, re-emerges on system level ICs to test some IC components such as timing critical datapaths or previously designed modules. Because fault simulation is computationally intensive, Viewlogic has added a network distributed fault simulation environment using techniques for load balancing that are unique in the industry, making fault simulation practical even for large designs. Parallel FaultSim dynamically allocates workload to selected computer processors to reduce the overall time needed to complete a specific fault simulation task. Performance gains of a four-processor run can be as much as 350%. For effective handling of large systems level ICs, it can also reduce memory requirements by up to 65% during compilation.

With system level ICs, the time and cost of locating silicon defects by traditional methods is becoming prohibitive. Advanced DFT methodologies, such as scan test, enable ATPG to reduce the test development time while increasing the quality of the manufacturing tests. Viewlogic's SHERLOC tool is used by test and failure analysis engineers to accurately predict the location of silicon defects following IC manufacturing. The first production release of SHERLOC is now available as an option to the Sunrise TestGen tools.

ScanPlanner is scheduled to be available in June 1997. The other new options to the Sunrise TestGen tool suite are available immediately. Pricing for the TestGen tool suite starts at $95,000.

Viewlogic Systems, Inc. is a worldwide supplier of electronic design automation software. The company's design tools enable electrical engineers to design state-of-the-art electronic products more efficiently, while reducing both development costs and time to market. The company offers software for both UNIX- and Windows-based computing platforms, along with a broad range of support services. Viewlogic is the first Computer Aided Engineering (CAE) software company in the world to achieve registration to ISO 9001/TickIT, the most comprehensive of the ISO quality standards. For more company information, the Internet home page address for Viewlogic is http://www.viewlogic.com . Viewlogic press releases are also available through the Company's News on Demand fax service by calling [phone].

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CONTACT: Karen Wills

Viewlogic Systems Inc.

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