ViewLogic Expands Leading-Edge ASIC Position with Datapath, Test and Sign-Off Solutions; Integrates Best-In-Class Point Tools Into Industry-Leading Solutions.

LAS VEGAS--(BUSINESS WIRE)--June 3, 1996--Viewlogic Systems, Inc. today announced ASIC design, verification and test solutions that eliminate critical bottlenecks of complex ASIC design. The company believes these solutions, which integrate Viewlogic's best-in-class technologies and strategic third-party tools, will improve designer productivity and reduce development time by up to 80 percent.

The announcements expand Viewlogic's technology leadership in ASIC design and represent the first step in the company's ASIC 2000 project, which was announced separately today. The project will combine Viewlogic's best-in-class point tools and industry-leading integration technologies into comprehensive design flows that solve the problems of complex ASIC design. Also toward that end, the company today announced its intention to support the Delay Calculation System -- a suite of redefined data-format and tool- interoperability standards, jointly defined by Open Verilog International and the CAD Framework Initiative aimed at supporting deep-submicron IC and ASIC design.

"Deep-submicron geometries, complex functional blocks and increasing device speeds wreak havoc on conventional ASIC design tool technologies and methodologies," said Will Herman, president and COO of Viewlogic Systems Inc. "Our long-standing leading-edge ASIC customer base gives us a clear view of what these designers need to realize the new generation of complex ASICs. Viewlogic is committed to solving the problems of complex ASIC design and brings the full weight of our best-in-class point tools and superior integration technology to provide solutions for our customers."

The Datapath Design Solution

Aimed at producing smaller, faster, compute-intensive ASIC designs, Viewlogic's Datapath Design Solution is centered on the breakthrough PathBlazer datapath synthesis tool. PathBlazer allows designers to explore and optimize datapath architectures with layout-accurate timing and area information. In so doing, PathBlazer eliminates the vicious timing iterations required by conventional synthesis, without being constrained by the limited architectures and technology-dependence of datapath compilers.

At the heart of PathBlazer's accurate timing capability is the MOTIVE technology from Viewlogic's Quad Design Group. As PathBlazer explores various architectures it performs a fast place and route on each implementation alternative and uses MOTIVE technology to evaluate the timing. This approach makes PathBlazer the most accurate synthesis tool available for datapath optimization. Moreover, PathBlazer users who later use MOTIVE technology for full-chip timing analysis will see a level of consistency not found in other solutions, where timing discrepancies cause delay and redesign.

"PathBlazer uses MOTIVE technology to evaluate timing and provide its synthesis engine with the information necessary to make intelligent optimization choices," said Chuck White, vice president of timing analysis at Quad. "Because the MOTIVE timing-analysis engine is embedded in PathBlazer, it has the necessary timing accuracy to optimize the architecture, placement, and timing of complex, deep-submicron datapath designs. This timing-driven approach results in higher performance designs and eliminates the synthesis/layout iterations required by other synthesis tools."

To complete the Datapath Design Solution, PathBlazer links to best-in-class tools for logic synthesis, full-chip floorplanning, and place and route. Links to Synopsys Inc.'s Design Compiler allow designers to use this tool for design blocks that are not datapath intensive. Employing the Design Exchange Format and Physical Design Exchange Format standard interfaces, PathBlazer passes datapath placement forward for incorporation into the full-chip floorplan and final layout.

"Synthesis tools can no longer be content to simply optimize logic and produce a netlist," said Dave Johannsen, chief architect for PathBlazer. "Conventional synthesis tools cannot optimize for timing because they can not accurately assess the speed of implementation alternatives. They don't have an accurate understanding of interconnect. So the deep sub-micron paradigm is that synthesis tools must produce and use layout information. What's needed is a unification of architectural design, synthesis, placement, and timing analysis. PathBlazer is the first synthesis product that does this."

In a related announcement, Viewlogic today announced a partnership with Motorola's Semiconductor Products Sector aimed at enhancing Viewlogic's datapath design solution and creating a next-generation design methodology that unifies the logical and physical design of deep-submicron ASICs.

The Verification Solution for ASIC Sign-Off

The second solution is a comprehensive ASIC sign-off methodology that enables designers and ASIC vendors to dramatically reduce their sign-off overhead. This solution enables designers to release an ASIC to manufacturing using either traditional simulation sign-off or the innovative timing analysis methodology pioneered by Viewlogic with leading ASIC vendors.

At the heart of the simulation sign-off solution is the Chronologic Verilog Compiled Simulator (VCS). The industry's performance leader for Verilog simulators, VCS also enjoys ASIC sign-off support from several leading ASIC vendors, including LSI Logic, Toshiba and Lucent Technologies. The VCS simulator last month increased its performance lead with the announcement of the Roadrunner technology option that boosts performance between five and 10 times that of the current version of VCS.

To enable the timing-analysis sign-off methodology, Viewlogic has added MOTIVE and integrates the Sunrise TestGen testability engine. This solution reduces verification time for sign-off by up to 80%.

Using this new methodology, design functions are verified through functional simulation (with either VCS or VCS/Roadrunner), while timing is verified using MOTIVE. High fault coverage is achieved through TestGen's automatic test-pattern generation.

"Test patterns from any ATPG tool must be verified with an ASIC vendor's sign-off simulator. VCS now enjoys growing support for ASIC sign-off. By linking TestGen with VCS, we can generate sign-off quality test patterns and avoid any glitches and time to market delays that may occur with other solutions," said Mark Milligan, vice president of the Sunrise Test business unit.

"ASIC designers do not have to give up performance when they progress from RTL to gate-level sign-off simulation using VCS," said Ghulam Nurie, director of marketing for the Simulation business unit. "They can get the benefits of Roadrunner's performance boost even at gate-level simulation when using timing analysis sign-off."

The ASIC Design-to-Test Solution

Viewlogic's ASIC Design-to-Test Solution focuses on linking industry-leading ASIC development tools to reduce customer time to market. This solution comprises Chronologic VCS simulation, Quad MOTIVE timing analysis, and Sunrise TestGen test-automation tools.

"As the leading provider of high-performance Verilog simulation, timing analysis, and test automation, Viewlogic is uniquely positioned to improve our customers' time to market with a solid design-to-test development solution," said Sunrise's Milligan. "By providing automated links between powerful best-in-class point tools, our customers will spend less time developing tool flows and will get their designs out faster."

With the ASIC Design-to-Test Solution, designers can verify test vectors with VCS, analyze timing for delay path testing with MOTIVE, and analyze testability and synthesize with Sunrise START tools. Test pattern generation is performed with Sunrise TestGen, and automatically prepared for vendor sign-off with VCS.

The ASIC Design-to-Test Solution also addresses the relationship between submicron timing effects and test quality. Timing-related manufacturing failures are becoming a major concern with the small-geometry silicon technologies now hitting the mainstream, and they are typically not being tested with current solutions. The ASIC Design-to-Test Solution links the popular Quad MOTIVE timing analysis tool the Sunrise PathTest product. MOTIVE identifies timing critical paths in a design, and PathTest automatically generates vector sequences to exercise these paths.

"MOTIVE quickly finds the timing paths in your design that are potentially of concern," said Quad's Chuck White. "It eliminates the need to create functional patterns to exercise timing critical paths and then perform logic simulation with full timing. That manual process is time consuming and hazardous because it is almost impossible to be sure you have covered all the cases."

Eliminating functional patterns for timing verification during the design enables analysis to be completed more quickly and accurately, but designers must still verify that those paths will actually function in silicon because manufacturing flaws can slow down critical paths. Without a dedicated verification test, designers don't find flaws until system test, or worse, when customers find the defects. Viewlogic's ASIC Design-to-Test solution takes the next step by automatically creating multi-cycle test patterns for those critical paths. These tests are then applied on the tester, ensuring that each part performs at the required design frequency and catching timing related manufacturing defects.

Sunrise TestGen is the industry leading test solution and includes testability analysis and synthesis, boundary-scan support, automatic test-pattern generation, fault simulation, and manufacturing-defect diagnosis. It contains modules for IDDQ current and path-delay testing, and network-distributed test-pattern generation.

Price & Availability

Viewlogic's Datapath Design Solution is available now to beta customers. The ASIC Design-to-Test and Verification for ASIC Sign-off solutions are available now. Prices for all of the solutions depend on configuration.

Viewlogic Systems, Inc. (NASDAQ: VIEW) is a worldwide supplier of electronic design automation software. The company's design tools enable electrical engineers to design state-of-the-art electronic products more efficiently, while reducing both development costs and time to market. The company offers software for both Unix- and Windows-based computing platforms, along with a broad range of support services. Viewlogic is the first Computer-Aided Engineering (CAE) software company in the world to achieve registration to ISO 9001/TickIT, the most comprehensive of the ISO quality standards. For more company information, the Internet home page address for Viewlogic is http://www.viewlogic.com. Viewlogic press releases are also available through Business Wire's News on Demand fax service by calling [phone]. -0-

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