Via modeling: accurate modeling can keep your vias from becoming problems, especially at high speeds. But watch that return current.

The via is more important to your interconnect arsenal than ever. PCB designers have to deal with high pin-count devices and shrinking PCB real estate, making use of the via almost mandatory. However, the through-hole via can have a significant impact on high-speed digital design.

Historically, at slower signaling speeds, vias were basically ignored by digital designers and treated as just another form of connection in the Z direction. Copper traces on signal layers acted as the horizontal wires and drilled holes, which where subsequently plated, acted as the wires in the vertical direction. Today, as signaling speeds move into the hundreds of megahertz and past 1 gigahertz, vias can no longer be ignored.

Vias can lead to all manner of problems:

* Impedance mismatches with other portions of the interconnect (traces).

* The creation of stubs.

* The discontinuity created in the return current path of the circuit.

These basic concepts are straightforward to anyone with a background in electronics. There are simple steps that can be taken to minimize the impact of vias. As always, simulation of the topology before and after layout is highly recommended. Let's take a look in more detail.

Circuit Topology

To understand the via's biggest impact on high-speed signaling, one must first understand the best circuit topology for high-speed signaling. If we start with wires in free space, an outbound signal wire, together with a dedicated return current wire that is tightly coupled with the outbound wire (e.g., as in a coaxial cable), we have a very good topology to maintain high signal quality, low radiation and high noise rejection. Designers don't need to know the physics behind this; they just need to use it as a reference for their thinking when they go to the PCB domain.

Recreating a coaxial cable on a PCB is best done by a using a trace over an undisturbed ground (reference) plane that is in close proximity to the signal layer. Most designers know this rule of thumb for high-speed digital boards: Maintain a complete unbroken reference plane at all cost. So why a solid plane, you ask?

According to Kirchhoff's current law, a current travels in a closed loop and on the path of least impedance. At slow speeds, the return path is the path of least resistance, but once we get to the megahertz range, the return path impedance is dominated by inductance. It takes less energy to create the electromagnetic fields if the outbound and inbound currents are very closely coupled, which happens if the return current flows directly above or below the outbound signal trace.

FIGURE 1 shows a simple example of a slot in the ground plane where the return current must detour around the slot. When designers deviate from this closely coupled system, the return current can not follow the same path as the outbound signal. When this happens, several things occur: Increased radiation as you increase the cross-sectional area of the current loop, an increase in the inductance of the circuit and the sharing of the return path with other signals, causing other common-mode problems.

[FIGURE 1 OMITTED]

Vias add a third dimension for return current, and there is no close proximity path in the vertical direction for the return path current to take unless the PCB designer creates one. This is, signal-wise, the biggest problem created when using vias. Ground planes act as great horizontal paths where the current can flow exactly under the outbound trace. But for the return current to move vertically, it must find an alternate path, either through the decoupling network and a nearby capacitor or component, a via used to short similar planes together, or by using the capacitance of the plane pairs. Electromagnetic guys call this a circuit discontinuity for this very reason--return current flow is discontinuous and there is an impedance change as well. Digital designers need to worry about the physical layout of their circuit in all three dimensions, specifically regarding return currents.

FIGURE 2 shows the various types of vias that are commonly used, with the predominate variety being a through-hole via. Unfortunately, the through-hole via is capable of creating the most problems, especially in thick backplane stackups, which produce a relatively long via.

[FIGURE 2 OMITTED]

The thicker the stackup, the longer the via and the sooner its effects begin to distort the signal. The outbound signal sees a bigger impedance discontinuity, and subsequently the lower the signaling speed where designers see this reflection (segments longer than about 1/6th of the rise time are "visible"). In addition, the longer via creates larger loops in the return current path, and even if care is taken to make sure the outbound signal and the return current are on adjacent layers, the long via creates a stub of significant length, producing reflections and possibly causing resonances.

Microvias, blind and buried vias, all require additional manufacturing steps for partial drilling and plating, and are less popular attempts to minimize the effects of vias. They limit the length to the specific distance between the layers that need connecting, produce shorter vertical connections, less inductance, less capacitance and no stubs. An additional benefit is that they also allow stacking of vias at the same XY location, producing denser designs with fewer layers.

Solution: A Signal Reference Plane

This is the best situation for high-speed signaling. Even though an interconnect requires multiple layers to move from driver to receiver, if it keeps the same reference plane (i.e., return current flows in the same plane regardless of which layer the signal is on), return current can flow closely coupled beneath the signal trace. FIGURE 3 shows a very simplified picture of this. Using a via to move the signal from layer 1 to layer 2 is safe since the reference plane for both of these layers is the ground plane on layer 3. A blind via would be best, but if designers had to use a through-hole via, it's important to recognize that a stub would exist and produce some unwanted effects.

[FIGURE 3 OMITTED]

There is still more to do to make sure the single reference plan is maintained. Designers must make sure the driver and receiver components are using the ground layer that the signal is referenced to. This is not a problem on a single ground/power plane stackup, but many systems today have several power/ground plane pairs. If the driver or receiver is referenced to ground in a different plane pair, the return current needs to make the transition to the reference plane. If there is not a short circuit via or specific bypass capacitor between those planes near the signal via, the return path detour could be significant. Designers need to keep in mind that the power system must be correctly decoupled, or a single bypass capacitor will not be able to bypass a broadband digital signal.

If the situation requires that the outbound signal transition through the board such that the reference plane changes, there are things that can be done to limit the impact oil the return current. Remember that the return current needs to find a path between the reference planes (see FIGURE 4). The preferred way is to use a short circuit via between the ground planes. Alternatively, designers can choose a bypass capacitor between planes near the signal via. Again, attention must be paid to the driver and receiver component references, as they still need to be referenced to the planes that are being used for the return current. Remember, too, that any via produces an impedance discontinuity for the outbound signal and can produce reflections or resonances.

[FIGURE 4 OMITTED]

Differential pairs are used to specifically create a closely coupled return path for the signal, eliminating most of the single-ended signaling problems (like the aforementioned twisted pair). However, even though each side of the differential pair has its own via, there are potential problems with impedance mismatches. One is the added capacitance of the via passing through the planes, and another occurs if there are any differences in the routing of either side of the signal pair. This can create currents in the reference plane to compensate for the difference between the pairs. Therefore, designers still need to provide a path for the return current to transition in the vertical direction, and the best option is to follow the rules mentioned earlier for single-ended signaling.

Modeling Via Impedance

Let's look at how vias are modeled electrically. By decomposing a via into a series of its physical structures, the inductance and capacitance of each type of structure can be calculated by well known formulas. FIGURE 5 shows that in a large through-hole via, there are a large number of structures that would affect the impedance calculation. Again, choosing one of the smaller alternate types of vias would reduce the structures and the resulting amount of inductance and capacitance. It is important to note that the physical decomposition does not take into account the inductance of the non-closely-coupled return current path.

[FIGURE 5 OMITTED]

Additional accuracy for this inductance in a simulation requires an understanding of the PCB topology around the via. Where the return current transitions vertically and the distance from there to the signal via will impact this value significantly. Few SI simulators take this into account unless a 3D field solver is used to model the whole vicinity around and including the via. Because it is very difficult to know exactly where the transition occurs, creating the model is a very tedious and error-prone task.

Vias can also cause EMI. As we discussed earlier, the via discontinuity causes a detour in the ground return current path, where the loop that the current takes during its detour basically becomes an antenna. The farther the return current has to go out of the way the larger the loop and radiation (|E|=Area*Current*[Freq.sup.2]). The steps discussed above minimize this return path detour and will reduce the resulting EMI. Another potential EMI problem occurs when a via transitions between plane pairs, which can act like a horizontal waveguide. This allows the radiation from the via to travel efficiently in the horizontal direction, causing crosstalk between vias. And when it reaches the edge of the board, it can produce EMI from the edge of the board.

Increasing IC package complexity is driving pin counts well above 1,000 pins and shrinking PCB real estate. The miniaturization required by portable electronic devices is forcing designers to use vias in large numbers. With clock speeds increasing it is important for both digital and PCB designers to understand the effects of vias. At all but the highest frequencies, there are straightforward methods that circumvent these effects. Signal integrity simulators are only just beginning to take into account ground return path effects in their modeling, so it is incumbent on the designer to check all high-speed signal paths for via issues. As the number of nets that need to be checked increases, EDA tools should provide computer-assisted checking of these paths for discontinuities.

DAVE KOHLMEIER is director of high-speed products at Mentor Graphics Corp. He can be reached at [e-mail].