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Verisity Donates Temporal Language to Open Verilog International; Temporal e Streamlines Interoperability.



Business Editors/High-Tech Writers

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--May 1, 2000

Verisity Ltd., the leading provider of functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task,  automation, today announced that it has donated the temporal subset of its e verification language to Open Verilog International (OVI OVI Ohio Volunteer Infantry
OVI Onderstepoort Veterinary Institute
OVI Open Verilog International
OVI Optically Variable Ink
OVI Ort von Interesse (German)
OVI Operating a Vehicle while Intoxicated
). As e is the defacto standard for functional verification automation, the donation is significant because it will provide the industry with a proven, mature format for standardization standardization

In industry, the development and application of standards that make it possible to manufacture a large volume of interchangeable parts. Standardization may focus on engineering standards, such as properties of materials, fits and tolerances, and drafting
. The subset will be given to the Formal Verification
"Verifiability" redirects here. For the Wikipedia policy, see Wikipedia:Verifiability.


In the context of hardware and software systems, formal verification
 Technical Subcommittee for consideration as the standard property language for formal model checking.

In a simulation environment, the temporal subset of the e language is used primarily to implement checkers checkers, game for two players, known in England as draughts. It is played on a square board, divided into 64 alternately colored—usually red and black or white and black—square spaces, identical with a chessboard. . In a model checking environment, temporal e is ideal for representing properties to be verified. As the model checking market growsmore users adopt the technology and more vendors offer their own solutionsthe need for a standardized standardized

pertaining to data that have been submitted to standardization procedures.


standardized morbidity rate
see morbidity rate.

standardized mortality rate
see mortality rate.
 language increases. The Formal Verification Technical Subcommittee's goal is to create a property language standard to make it easier for engineers to incorporate model checking into their existing environments.

"Since model checking and simulation must co-exist in a single verification methodology, having a single source to drive both engines streamlines interoperability The capability of two or more hardware devices or two or more software routines to work harmoniously together. For example, in an Ethernet network, display adapters, hubs, switches and routers from different vendors must conform to the Ethernet standard and interoperate with each other. ," said Dr. Vassilios Gerousis, chairman of OVI's Technical Coordinating Committee. "The potential of model checking technology for verifying complex IC and system-on-chip designs is very exciting, but the tools available today are perceived to be too hard to use and the languages are proprietary and very complex. Verisity's e language has all the right technical capabilities, and can be used to drive both simulation and model checking."

"OVI has a long and successful track record for driving standards that are beneficial to users," said Moshe Gavrielov, chief executive officer for Verisity. "We are committed to establishing e as a standard and this donation is a significant step in our standardization roadmap."

The Road to Standardization

Traditional design languages--such as Verilog and VHDL--were created for hardware design and are not well suited for verification of today's complex integrated circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for , system-on-chip and system designs. C and C++ have emerged as alternatives, but are also not ideal since they were created for software design and lack sufficient hardware constructs as well as verification constructs. Verisity created the e language specifically for verification automation. The market has made it the de facto standard Hardware or software that is widely used, but not endorsed by a standards organization. Contrast with de jure standard.

de facto standard - A widespread consensus on a particular product or protocol which has not been ratified by any official standards body, such as ISO,
, thereby making it the obvious choice for standardization.

Verisity's efforts towards standardizing e has thus far been focused on meeting the criteria to become a successful industry standard. Verisity believes that making e a successful standard includes all of the following criteria:

- De facto [Latin, In fact.] In fact, in deed, actually.

This phrase is used to characterize an officer, a government, a past action, or a state of affairs that must be accepted for all practical purposes, but is illegal or illegitimate.
 usage--the format must be in use by a significant

part of the market, including strategic customers that

influence the marketplace. Verisity's customer list includes

all major players in the communications, semiconductor and

intellectual property arenas. Verisity's e language is

currently the de facto standard, holding over 77 percent

market share.

- Third-party pull--there must be a large pull from customers

and third parties to interoperate with the format. In other

Verisity news today, the company announced that it is

licensing the complete e language, and Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services.

http://cadence.com/.

See also Verilog.
,

Inc. and Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create.  Corp. are the first companies to

license the language (see related press releases dated

5/1/00).

- Interested standards bodies--there must be interest in

developing the format into a formal standard from standards

organizations. Today's news indicating OVI's acceptance of the

temporal e donation marks a significant step in Verisity's

roadmap to standardization. The donation is subject to the

approval of the Office of the Chief Scientist Office of the Chief Scientist may refer to:
  • Office of the Chief Scientist (Australia), Department of Education, Science and Training (Australia). Jim Peacock was appointed in March 2006.
  • Office of the Chief Scientist (Canada), Health Canada.
 in Israel.

About Verisity

Verisity Ltd. develops, markets, and supports functional verification automation solutions for engineers to validate complex communications designs and other advanced electronic systems. The company's products automate traditionally manual processes and have enabled customers to cut verification schedules by up to two thirds, shaving months off total project schedules. Verisity is the market leader with over 77 percent market share. The company is headquartered in Rosh-Ha'ain, Israel and has its main sales and marketing office in Mountain View, CA. Verisity's research facilities are also located Israel and California. The company currently employs over 120 people. For more information, see Verisity's web site at www.verisity.com.

Verisity is a registered trademark of Verisity. All other trademarks are the property of their respective holders.
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Publication:Business Wire
Geographic Code:1USA
Date:May 1, 2000
Words:710
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