Verific ships first commercially available SystemVerilog parser.

Verific Design Automation, a provider of Verilog and VHDL front ends for electronic design automation (EDA) applications, recently announced that it is shipping the first commercially available SystemVerilog parser.

Written in platform-independent C++ for easy integration, consistency and efficiency, Verific's SystemVerilog Parser supports the entire SystemVerilog 3.1 language definition, with the exception of SystemVerilog Assertions, for which it supports 3.1a. Since the SystemVerilog Parser began shipping October 1, early adopters are using it in formal verification software and hardware description language (HDL) visualization tools.

"The market is quickly moving to SystemVerilog and we respond immediately to market demands," says Rob Dekker, president of Verific. "Supporting SystemVerilog with our SystemVerilog Parser gives EDA developers the means to support this powerful language inside their design tools, and hence providing a large group of end-users, essentially design engineers, with access to the language. If the end users want it, their EDA tools provider can now deliver. "

SystemVerilog, the hardware description and verification language (HDVL) standard, is an extension of the established IEEE 1364-2001 Verilog language, and was developed by Accellera to improve productivity in the design of large gate count, intellectual property (IP)-based, bus-intensive chips. It is targeted primarily at the chip implementation and verification flow, with links to the system-level design flow.

"As the key driving force behind SUPERLOG, which became SystemVerilog, it's heartening to see the ecosystem develop around the SystemVerilog language," remarks Simon Davidmann. "The existence of Verific's SystemVerilog Parser will further speed adoption of the language and allow new tools to be created sooner, as EDA companies can focus on their added value. Verific is leading the way in helping the industry race forward in developing SystemVerilog tools."

Verific's SystemVerilog Parser includes a parser, analyzer and elaborator. It parses and analyzes the entire SystemVerilog 3.1 language definition. For assertions, it follows the SystemVerilog 3.1a syntax. After parsing, a complete parsetree is available. Static elaboration and register transfer level (RTL) elaboration for synthesis is fully supported for the Verilog 2001 subset, extended with support for many of the new SystemVerilog constructs. Additional elaboration is planned for intermediate releases between now and the end of the year.

The parser has been tested with an internally developed SystemVerilog test suite, and has also been verified with simulators provided by partnerships with Synopsys (Nasdaq:SNPS) and Mentor Graphics (Nasdaq:MENT).

The SystemVerilog Parser is shipping now and runs on Solaris, HP-UX, Linux and Windows platforms. The U.S. pricing starts at $100,000 for a perpetual, royalty-free, source-code license of the parser and analyzer. Pricing for a time-based license starts at $4,000 per month. Additionally, Verific offers an upgrade program for existing Verilog 2001 customers.