Verific Adds OpenAccess Interface to Product Portfolio; Interface Links SystemVerilog, VHDL to OpenAccess 2.2 database.ALAMEDA Alameda (ăləmē`də, –mā`də), city (1990 pop. 76,459), Alameda co., W central Calif., on an island just off the eastern shore of San Francisco Bay; settled 1850, inc. as a city 1884. , Calif. -- AT DATE 05 BOOTH #E6400 Verific Design Automation, the leading provider of Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. front ends for electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) applications, today announced immediate availability of an interface between its hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) Component Software and the OpenAccess database. This new OpenAccess interface offers a link to Verific's HDL parser A routine that analyzes a continuous flow of text-based input and breaks it into its constituent parts. See parse. (language) parser - An algorithm or program to determine the syntactic structure of a sentence or string of symbols in some language. for Verilog, SystemVerilog and VHDL, offering fast netlist import, along with full register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) support to the OpenAccess 2.2 database. Says Steve Schulz, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Si2: "This announcement is further evidence that marketplace momentum for OpenAccess continues to grow, now expanding in scope up through SystemVerilog, thanks to OpenAccess v2.2 support in Verific's commercial HDL parsers. This is good news for Verific and their licensees, good news for end users, and good for Si2's mission of open EDA interoperability. In short, it's good for business." The interface, developed in partnership with Silicon Navigator, will be demonstrated in Booth Number E6400 this week at Design Automation and Test Europe (DATE 05) beginning tomorrow -- Tuesday, March 8 -- at Messe Munich, Germany. "Semiconductor companies are demanding OpenAccess support," remarks Verific's President Rob Dekker, who adds that Silicon Navigator became the perfect partner to help develop this interface as a company dedicated to providing EDA components around the standard. J. George Janac, Silicon Navigator's CEO, agrees. "For OpenAccess to become successful, the industry needed a high-performance path from Verilog and VHDL RTL and netlist. Verific provides key components needed by Open Access, and in addition supports SystemVerilog, making it even more attractive for design teams preparing for the future." Developed for flexibility, the Verific interface can be used with Verific's native netlist data structures. Alternatively, synthesized register transfer level (RTL) code can be stored in the OpenAccess database. OpenAccess is a community effort to provide interoperability among integrated circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for (IC) design tools through an open standard data applications programming interface (API (Application Programming Interface) A language and message format used by an application program to communicate with the operating system or some other control program such as a database management system (DBMS) or communications protocol. ) and reference database. Verific's OpenAccess interface, written in C++, follows Si2's OpenAccess API specification and database code manual. It is available now to its licensees, and shipped free of charge with its standard HDL component software. For more details, contact Rick Carlson, Verific's vice president of sales. He can be reached at (970) 946-1755 or via email at rick@verific.com. Or, visit Verific's website located at: http://www.verific.com. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based Verilog, SystemVerilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 30,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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