Verific Adds Liga Systems to Growing Customer List; Verific HDL Component Software Serves as RTL Front End to Liga Systems' New Hybrid Simulator.ALAMEDA, Calif. -- Electronic Design Automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) newcomer Liga Systems Inc. announced today that Verific Design Automation's hardware description level (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) Component Software will serve as the register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) front end for NitroSIM(TM), its Hybrid Simulator. Liga Systems, an EDA company focused on delivering lightning-fast RTL simulation to the desktop, has integrated Verific's Verilog parser A routine that analyzes a continuous flow of text-based input and breaks it into its constituent parts. See parse. (language) parser - An algorithm or program to determine the syntactic structure of a sentence or string of symbols in some language. , analyzer and elaborator with its Hybrid Simulator. Verific's HDL component software packages, which include an RTL database, are written in platform-independent C++ that compiles on Solaris, HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations. (operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. , Linux and Windows platforms. All products are licensed as source code and come with online support and maintenance. "Liga Systems turned to Verific for its industry-leading HDL Component Software because it helped us save invaluable time and effort," says Henry Verheyen, Liga Systems' chief executive officer. "Our team has found the Verific code to be very clear, providing good value as we extend its use for simulation. Using Verific's front-end technology, we were able to bring up a complex Verilog RTL compiler quickly, reducing our time to market, while achieving a high quality product." "It gives us great pleasure to work with Liga Systems as it brings its first product to market," adds Michiel Ligthart, Verific's chief operating officer Chief Operating Officer (COO) The officer of a firm responsible for day-to-day management, usually the president or an executive vice-president. . Verific's entire line of HDL Component Software will be demonstrated in Booth #3345 during the 43rd Design Automation Conference (DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ) July 24-27 at San Francisco's Moscone Center. To schedule a demonstration during DAC, visit Verific's website located at: http://www.verific.com. Or, contact Rick Carlson, Verific's vice president of sales. He can be reached at (970) 946-1755 or via email at rick@verific.com. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and PSL/Sugar front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
|
||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion