Vantis Unveils New Architecture for High-density CPLD Products.SUNNYVALE, Calif.--(BUSINESS WIRE)--June 7, 1999-- --New Architecture Combines High Density and High Performance While Maintaining the Successful MACH 4 Family's Ease-of-Use Features-- Vantis today announced a new architecture for high-density CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. products. Code-named Godfather, the architecture uses elements of the MACH(R) 4 family connected by a new hierarchical switch matrix, providing high performance coupled with ease-of-use features. Initially, Vantis will use this architecture to provide devices up to 1,024 macrocells. The Godfather architecture will be manufactured using Vantis' advanced 0.25-micron (Leff) electrically erasable e·ras·a·ble adj. 1. Capable of being erased: erasable ink. 2. Capable of producing something that can be erased: an erasable pen. CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. process technology. According to according to prep. 1. As stated or indicated by; on the authority of: according to historians. 2. In keeping with: according to instructions. 3. the company, customers in the telecommunications and networking industries are driven to further integrate their systems to achieve increased functionality while being constrained to the same physical space. "Existing high-density solutions such as FPGAs or ASICs force designers to compromise either time to market or performance," said Andy Robin Andy Robin is a writer and director who worked on NBC's Seinfeld for several seasons with collaborator Gregg Kavet, penning many episodes, including The Junior Mint, The Jimmy, and The Fatigues, which won the Writers Guild Award for Episodic Comedy. , vice president of Marketing at Vantis. "The Godfather architecture allows designers to achieve higher integration without having to make these sacrifices." Godfather Architecture The macrocell forms the base element of the Godfather architecture. Macrocells are clustered into an array of SuperBlocks(TM), an enhanced version of the popular MACH 4 PAL(R) block. These are interconnected with an innovative, two-level hierarchical routing hierarchical routing - The complex problem of routing on large networks can be simplified by breaking a network into a hierarchy of smaller networks, where each level is responsible for its own routing. scheme. SuperBlocks Traditionally, CPLDs have been built up from PAL blocks with approximately 34 inputs and 16 macrocells. The Godfather architecture utilizes an integrated PAL block structure with 80 inputs and 32-macrocells that Vantis refers to as a SuperBlock. This integrated structure enables design engineers to implement 64-bit wide functions within a single block, with a single level of delay and achieve significantly higher performance. The macrocells used within the SuperBlock are a superset A group of commands or functions that exceed the capabilities of the original specification. Software or hardware components designed for the original specification will also operate with the superset product. However, components designed for the superset will not work with the original. of those used in Vantis' MACH 4 family. Key enhancements include the ability to provide extra wide product term allocation per macrocell, more flexible clocking, independent set and reset, and clock enable for each macrocell, further increasing design flexibility and ease of use. SpeedLocked Tiered Routing In traditional CPLD architectures, the central switch matrix increases exponentially in size with additional logic resources. The Godfather architecture uses a hierarchical routing scheme called SpeedLocked Tiered Routing(TM) (STR STR abbr. synchronous transmitter receiver ) to interconnect its SuperBlocks. This architecture allows expansion to higher densities while preserving the speed, invariant (programming) invariant - A rule, such as the ordering of an ordered list or heap, that applies throughout the life of a data structure or procedure. Each change to the data structure must maintain the correctness of the invariant. timing, and ease of design associated with smaller devices. The innovative Godfather architecture captures all of the benefits of a hierarchical design with just two levels of hierarchy: the Segment Switch Matrix(TM) (SSM SSM abbr. surface-to-surface missile ) interconnects four SuperBlocks into a 128-macrocell grouping called a Segment; the Global Switch Matrix(TM) (GSM) interconnects these Segments. This elegant architecture continues the Vantis tradition of providing easy-to-use, high-performance design solutions. Timing Model The Godfather timing model supports two types of requirements: SpeedLocked(TM) timing for fixed, predictable pin-to-pin delays or performance timing for high-performance, multi-level logic designs. The SpeedLocked timing model assumes inputs are routed through the GSM interconnect, allowing access to any available Segment with no additional delay adder adder: see viper. adder Any of several venomous snakes of the viper family (Viperidae) and the death adder, a viperlike elapid. Vipers include the common adder, puff adders, and night adders. Adders occur in Europe, Asia, Africa, and Australia. . This provides excellent pin-locking and pin-placement capabilities. The performance timing model utilizes a fast path that is available between inputs and the Segment. This allows designers to achieve higher performance on sections of their designs that can be implemented within a single Segment. Phase Locked Loops (PLLs) The Godfather architecture contains four global clocks that can be used by each macrocell within the part. In addition, devices designed using this architecture will also contain up to two PLLs. These PLLs will provide reduced set-up and clock-to-out times, as well as the capability to multiply an external clock by two or three times for the highest performance and flexibility. Software Support The Godfather architecture will be supported by Vantis' DesignDirect(TM) software. This software is available in PC and workstation versions capable of entry in VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , Verilog, ABEL Abel, son of Adam and Eve, in the Bible Abel, in the Bible, son of Adam and Eve, a shepherd, killed by his older brother, Cain; in the Gospel of St. Matthew, mentioned as the first martyr. , and schematic formats. Additionally, DesignDirect software supports RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; , functional, and timing simulation. It also interfaces with tools from most of the major EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. vendors including Cadence, Exemplar, Mentor, Model Technology, Synopsys, Synplicity, and Viewlogic. Product Availability Initially, Vantis will use this architecture to extend its current CPLD offering up to 1,024 macrocells. Vantis expects to sample the first products in this density range during the beginning of 2000 with software availability planned in Q4 1999. This architecture also provides Vantis with the capability to create higher-density devices that will be provided in accordance with customer demand. About Vantis Vantis provides high-performance programmable logic See PLD. solutions for communications, computing and industrial applications. Vantis focuses on designing and marketing advanced programmable logic products that satisfy the speed, density and ease-of-use requirements for today's logic designs. Vantis is headquartered in Sunnyvale, California, and has offices in the United States, Europe, Japan, and the Pacific Rim. Cautionary Statement This news release contains forward-looking statements regarding programmable logic products and software that involve risks and uncertainties that could cause actual results to differ materially, including, the impact of competitive products and pricing, the timely development and availability of products, software tools and wafer fabrication process technologies, the timely acquisition of wafer fabrication services, the effect of changing economic conditions, and such risks and uncertainties detailed from time-to-time in the SEC reports of Advanced Micro Devices, Inc. World Wide Web: Press announcements and other information about Vantis are available on the Internet via the World Wide Web. Type http://www.vantis.com at the URL URL in full Uniform Resource Locator Address of a resource on the Internet. The resource can be any type of file stored on a server, such as a Web page, a text file, a graphics file, or an application program. prompt. Note to Editor: Readers may obtain additional information by calling 1 888-826-8472. SpeedLocked, SpeedLocking, SpeedLocked Tiered Routing, Segment Switch Matrix, Global Switch Matrix, SuperBlock, DesignDirect, Vantis and the Vantis logo are trademarks and PAL and MACH are registered trademarks of Vantis Corporation. General Notice: Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. |
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