VERPLEX SHIPS FULL-CHIP FORMAL RTL DESIGN VERIFICATION TOOL THAT CUTS LEARNING CURVE.Verplex(TM) Systems, Inc., known for its formal verification
In the context of hardware and software systems, formal verification software, has unveiled BlackTie(TM) functional checker check·er n. 1. a. One, such as an inspector or examiner, that checks. b. One that receives items for temporary safekeeping or for shipment: a baggage checker. 2. , a full-chip, multi-million gate capacity tool that accelerates the verification of system-on-a-chip (SOC (System On a Chip) The electronics for a complete, working product contained on a single chip. While a microcontroller includes all the hardware components required to process instructions, an SoC includes the computer and all required ancillary electronics. ) designs. BlackTie was designed to be easy to use, eliminating the learning curve normally associated with formal register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) design verification technology. It provides a means for exhaustive verification early in the design cycle when changes are easily fixed and less costly, and offers designers full-chip speed and capacity. In a recent customer engagement, for example, it verified more than 300,000 functional properties of a 2.7 million gate design in approximately 20 minutes using a standard Unix workstation. |
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