Ultra-thin, loaded epoxy materials for use as embedded capacitor layers: use of <25 [micro]m high capacitance power-ground cores can eliminate hundreds of discrete capacitors, not to mention improving signal integrity and EMI.

3M began developing embedded capacitor materials in the mid 1990s. 3M has been involved in an embedded capacitor DARPA program, the NCMS Embedded Distributive Capacitance (EDC) consortium and most recently, the NIST Advanced Embedded Passives Technology (AEPT) consortium. The EDC consortium focused strictly on embedded decoupling capacitance using laminate materials as power-ground cores. The AEPT program focused on embedded resistors and capacitors. For capacitors, not only was distributed capacitance studied but also singulated (discrete) capacitors. 3M supplied ultra-thin, loaded laminates to both consortia. The ultra-thin laminates consisted of an epoxy dielectric loaded with sub-micron non-fired barium titanate ceramic particles, which was sandwiched between two layers of 1 oz. (35 [micro]m) copper. Some of the more important material properties of this novel material (C-Ply) are shown in TABLE 1.

These consortia fabricated PCBs with a number of embedded capacitor materials to test board processing compatibility, reliability and electrical performance. The ultra-thin, loaded material was found to be compatible with all board processing including laser ablation (although some of the early PCB process steps had to be refined slightly to improve material transport of the thin and flexible material). No significant reliability issues were identified in boards fabricated with the ultra-thin material in either one of these consortia of by internal testing performed outside of these consortia. Some of the common industry tests under which the material was tested are shown in TABLE 2.

Finally, the consortia reviewed electrical properties of the embedded capacitor materials, particularly high frequency performance. In the NCMS EDC consortium, all embedded capacitor laminate materials tested were found to be better than surface mount discrete caps at high frequency (>1 GHz). However, the ultra-thin, loaded material was found to greatly outperform all other embedded capacitor laminate materials and SMT discrete capacitors over the entire 1 MHz to 5 GHz frequency range studied (FIGURES 1 and 2 and TABLE 3). The substantial high frequency performance improvement seen is due to the high capacitance density and more importantly, to the low self-inductance of the ultra-thin material.

The high-frequency electrical performance advantages of loaded, ultra-thin dielectric laminate material has been confirmed by test results in the NIST AEPT consortium as well as in outside tests. Istvan Novak of Sun Microsystems has done extensive work in comparing this ultra-thin, loaded material to commercially available material. Per Figure 1, the 8 [micro]m material has much lower impedance over the entire frequency range measured. In addition, the ultra-thin material has no post-resonance impedance spikes that can be seen in the 50 and 25 [micro]m materials. These large impedance spikes caused by board resonances generate noise on the power bus that can interfere with switching, create signal integrity issues and can also generate EMI (FIGURE 3).

[FIGURES 1-3 OMITTED]

Recent Testing

More recently, OEMs have looked into the use of more costly, low inductance discrete capacitors (in addition to traditional discrete capacitors) to solve decoupling issues. Data show that while these low inductance capacitors reduce more noise at higher frequencies than do traditional discrete capacitors alone, they do not work as well as using ultra-thin laminate materials as power-ground cores (FIGURE 4). Finally, when ultra-thin, loaded laminate materials are used, there is no difference in power bus noise, regardless of whether low inductance caps are added to the design. This is not a surprise because the novel material provides the desired low impedance decoupling across all frequencies.

[FIGURE 4 OMITTED]

The electrical performance advantages of ultra-thin loaded laminates when used as power-ground cures have been well documented and widely accepted. It has also been widely accepted that ultra-thin materials with high capacitance can be used to replace discrete capacitors. However, the question has always been, how much discrete capacitance can be removed?

The work done in the NCMS EDC consortia and data shared by OEM testing give a first look at answering this question. A total of five designs (including the NCMS EDC TV1) have used 3M's ultra-thin, loaded laminate material to replace surface mounted discrete decoupling capacitors. In most cases, a conservative amount of discrete decoupling capacitance was removed and the boards tested at the system level for functionality. In all cases, the boards were found to be functional. In some cases, additional capacitors were removed and the boards retested. Again, all boards were found to be functional. It can be seen that even though a conservative amount of capacitance was removed in some cases, the ratio of discrete capacitance removed to ultra-thin capacitance is still extremely high (TABLE 4).

This data suggest that if an ultra-thin power-ground core(s) supplies at least a couple hundred nanofarads of capacitance with a very low impedance, a very large number of surface-mounted discrete decoupling capacitance can be removed. It is strongly believed that all discrete decoupling capacitors under 0.1 [micro]F can be removed as well as the majority of 0.1 [micro]f decoupling capacitors. For high-speed digital designs, this can result in the removal of hundreds of discrete capacitors. This is also very significant for portable products. Portable products typically have far fewer discrete power supply decoupling caps than high-speed digital products. However, space is at such a premium that ultra-thin power-ground materials with high capacitance have generated a large interest in this market.

Two of these designs were tested for power bus noise and compared to baseline product with thin (50 [micro]m) FR-4 power-ground cores (and all discrete decoupling capacitors). In one case, the ultra-thin material power bus noise was slightly lower than the baseline design and in one case it was substantially lower (one-third the peak-to-peak noise). EMI was also tested on two ultra-thin designs (testing is ongoing on two additional designs) for comparison to baseline product with thin FR-4 power-ground cores. In one case, the ultra-thin material had slightly lower EMI, and in one case the EMI was significantly lower.

TABLE 1. Ultra-Thin Material Properties

Dielectric material:    Ceramic-filled epoxy

Capacitance/unit area:  4-10 nF/[in.sup.2] (10 nF/[in.sup.2] at 8
                        [micro]m thickness)

Capacitance tolerance:  +/-10%

Dielectric constant:    16

Dissipation factor:     0.005 (1 kHz)

Operating temperature:  -40 to 130[degrees]C ("X7R" behavior over this
                        range)

Dielectric strength:    130V/[micro]m

Breakdown voltage:      >100 V (for 16 [micro]m thickness)

TABLE 2. Reliability Testing

Thermal cycle/Thermal shock

Elevated temperature and humidity (with and without bias)

Solder floats/Multiple reflow

Mechanical (bend)

ESD

TMA 260 (delamination)

TABLE 3. TV1 Peak-to-Peak Noise Measurements

TYPE OF BOARD             NOMINAL CAPACITANCE (NF)  VPP (MV)

FR-4 with SMT decoupling           330                 214
BC2000 (50 [micro]m)                 3               1,740
EmCap (100 [micro]m)                13                 712
HiK (40 [micro]m)                   10                 816
C-Ply (5 [micro]m)                 107                  89

Courtesy of UMR

TABLE 4. Replacement of Discrete Capacitance

DESIGN     DISCRETE CAPACITANCE           ULTRA-THIN P/G
               REMOVED (NF)              CAPACITANCE (NF)

EDC TV1             330                        105
OEM A             12,600                       300
OEM B              6,310                       210
OEM C              3,180                       300
OEM D             52,900                      1,969

DESIGN       RATIO OF DISCRETE    % OF TOTAL DISCRETE DECOUPLING
           REMOVED TO ULTRA-THIN      CAPACITANCE REMOVED *

EDC TV1             3.1                        100%
OEM A              42.0                         NA
OEM B              30.0                        >60%
OEM C              10.6                        >75%
OEM D              26.9                        >75%

* Does not include low frequency bulk capacitors. NA: not available

ACKNOWLEDGMENTS

The author would like to thank the following individuals for providing input to this paper: Istvan Novak, Sun Microsystems; Todd Hubing, University of Missouri-Rolla; Bob Greenlee, Merix; Glenn Walther and Daniel Dotiu, Multek; Rick Charbonneau, StorageTek; Doug Lamond and John Grebenkemper, H-P; Seokkyu Lee, Samsung Electro-Mechanics.

BIBLIOGRAPHY

J. Peiffer, B. Greenlee and I. Novak, "Electrical Performance Advantages of Ultra-Thin Dielectric Materials Used for Power-Ground Cores in High Speed, Multilayer Printed Circuit Boards," IPC Printed Circuits Expo Proceedings, March 2003.

M. Xu, T. Hubing, J. Chen, T. Van Doren, J. Drewniak and R. DuBroff, "Power-Bus Decoupling With Embedded Capacitance in Printed Circuit Board Design," IEEE Transactions on Electromagnetic Compatibility, vol. 45, no. 1, February 2003.

J. S. Peiffer, NIST Advanced Embedded Passives Technology (AEPT) seminar, January 2003.

B. Greenlee, "Processing Thin Core Capacitor Materials," IPC Printed Circuits Expo Proceedings, March, 2002.

B. Greenlee, "Frequently Asked Questions for Printed Circuit Board Fabricators," DesignCon Proceedings, January 2002.

I. Novak and V. St. Cyr, "Frequently Asked Questions for Original Equipment Manufacturers," DesignCon Proceedings, January 2002.

R. Charbonneau, "NCMS Embedded Decoupling Capacitance Project," DesignCon Proceedings, January 2002.

J. S. Peiffer, "Fabrication of Embedded Capacitance Printed Circuit Boards," IPC Printed Circuits Expo Proceedings, April 2001.

J. S. Peiffer, "A Novel Embedded Cap Material," PC FAB, vol. 24, no. 2, February 2001.

J. S. Peiffer, "Embedded Capacitor Material Evaluation," Apex Proceedings, January 2001.

National Center for Manufacturing Sciences, "Embedded Decoupling Capacitance (EDC) Project Final Report," December 2000.

Ed. This article is adapted from the IPC National Conference on Embedded Passives, and is used with permission of the author.

JOEL S. PEIFFER is an engineering specialist with the 3M Corporate Research Materials Lab (for more information: 3m.com/us/electronics_mfg/microelectronic_packaging/ materials/index.jhtml). He can be reached at 651-575-1464; [e-mail].