Ultra Low-power ISP Flash & Logic For 8051 Systems; 5-V ISP Flash ZPSDs Draw 88% Less Power Than Alternative Solutions.FREMONT, Calif.--(BUSINESS WIRE)--May 3, 1999-- WSI See wafer scale integration. today introduced five new zero-power ZPSD813F MCU (1) (MicroController Unit) A computer on a single chip. See microcontroller. (2) (Multipoint Control Unit) A device that is used to moderate a videoconference of three or more end points (users at computers or groups of users support ICs that add external in-system programmable Refers to programmable logic chips (PLDs) that are programmed after they are attached to the circuit board. Also called "in-circuit programmable," devices that use static RAM (SRAM) are in-system programmable by nature because they are loaded at startup. See PLD. (ISP (1) See in-system programmable. (2) (Internet Service Provider) An organization that provides access to the Internet. Connection to the user is provided via dial-up, ISDN, cable, DSL and T1/T3 lines. ) flash memory and programmable logic See PLD. to 5-volt, 8-bit CISC (Complex Instruction Set Computer) Pronounced "sisk." The traditional architecture of a computer which uses microcode to execute very comprehensive instructions. designs without appreciably increasing the power drain. For example, adding 128 Kbytes of flash memory, a second 32 Kbyte flash memory to enable concurrent ISP, and an EPM EPM equine protozoal myeloencephalitis. 7064 CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD. to a 5-volt system with a 4 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. MCU clock will increase the power drain by 30.7 mA. Using the EasyFLASH(TM) ZPSD813F4 to add this same functionality will increase the power drain by only 3.7 mA -- 88% less than the discrete solution. ZPSD813F devices result in a small-footprint, two-chip, 100% in-system programmable solution that is idea for wire telecommunications, portable test equipment, and other space- or power-constrained applications. According to according to prep. 1. As stated or indicated by; on the authority of: according to historians. 2. In keeping with: according to instructions. 3. David Raun, WSI's Vice President of Marketing, "Eight-bit CISC microcontrollers, like the 8051, are the work horses of embedded systems designs. However they have some limitations in accommodating designs that need in-system programmability, that have a lot of product features implemented in software, that use high-level languages, or that include an OS kernel. Although a few single-chip MCUs offer ISP flash, they rarely have enough to store these large programs. "When this happens," Raun explained, "designers are forced to use external memory. If they need ISP capability, a second flash memory will be required, plus some programmable logic for address decoding and re-mapping. Since the 8051 architecture will not allow writes to program space, effecting in-system programmability will require some very complicated firmware. The 64 Kbyte limit on addressable Reachable. When something is addressable, it can be identified and manipulated independently of its surroundings. For example, screen pixels and RAM memory are addressable. Each of the screen's picture elements can be individually turned on and off, and each of the memory's bytes can be memory will also require some page logic. Adding these extra chips, increases board size and power drain and can add several weeks to the product development cycle. Some systems just can't afford it. "We developed our 5-volt EasyFLASH(TM) ZPSD813F devices to solve the problems associated with adding ISP flash to 8051 designs. They provide a very low power, small footprint, easily implemented solution for any design that needs external ISP flash and/or logic. The parts automatically handle memory paging. They automatically reclassify Verb 1. reclassify - classify anew, change the previous classification; "The zoologists had to reclassify the mollusks after they found new species" class, classify, sort out, assort, sort, separate - arrange or order by classes or categories; "How would you MCU address space, so ISP is effortless. And they have a programmable MCU interface that can be configured in a few seconds to work with virtually any 8-bit CISC microcontroller. They are the only flash memories to offer a JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group interface that eliminates the headaches associated with first-time programming. These features, combined with their extremely low power drain make them idea for any battery operated system," Raun concluded. Five Architectures Available - ZPSD813F devices are available in a variety of architectures, all of which offer 128 Kbytes of 100% ISP flash memory, a 3,000 gate CPLD, extra I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output , a JTAG programming interface and a programmable MCU interface, plus varying combinations of flash EEPROM (Electrically Erasable Programmable ROM) A rewritable memory chip that holds its content without power. Although EEPROMs spawned flash memory, EEPROMs are byte addressable at the write level, whereas flash chips must erase a block of bytes before rewriting. and SRAM See static RAM. SRAM - static random-access memory , as follows: -0-
Main Second
Device CPLD Flash Array Flash Array EEPROM SRAM
PSD813F5 3,000 gates 128 Kbytes ---- ----
PSD813F4 3,000 gates 128 Kbytes 32 Kbytes ----
PSD813F3 3,000 gates 128 Kbytes ---- ---- 2 Kbytes
PSD813F2 3,000 gates 128 Kbytes 32 Kbytes ---- 2 Kbytes
PSD813F1 3,000 gates 128 Kbytes ---- 32 Kbytes 2 Kbytes
ZPSD Discrete
Power Solution
Device Drain(1) Power(2)
PSD813F5 3.7 mA 30.1 mA
PSD813F4 3.7 mA 30.7 mA
PSD813F3 3.7 mA 30.6 mA
PSD813F2 3.7 mA 31.1 mA
PSD813F1 3.7 mA 31.1 mA
Enhanced JTAG Interface Provides Ultra-quick Serial ISP - ZPSD813F devices are the world's first flash-NVM-based devices to offer a JTAG interface for first-time and subsequent serial in-system programming (ISP). Conventional first-time in-system programming can be very difficult to implement, requiring a very slow SPI (1) (Stateful Packet Inspection) See stateful inspection. (2) (Service Provider Interface) The programming interface for developing Windows drivers under WOSA. interface or UART (Universal Asynchronous Receiver Transmitter) The electronic circuit that makes up the serial port. Also known as "universal serial asynchronous receiver transmitter" (USART), it converts parallel bytes from the CPU into serial bits for transmission, and vice . ZPSD813F devices are the world's only flash-NVM device to provide an enhanced JTAG interface that quickly and painlessly allows first-time programming. WSI' FlashLink programmer also can be used to do field-updates of ZPSD813F devices via the JTAG interface, using a notebook computer. Several features in the ZPSD813F JTAG interface speed up device programming. These include embedded programming algorithms, address incrementing, an embedded state machine, a two-stage data pipeline and two additional, optional JTAG pins. Conventional 4-pin JTAG programming inefficiently counts the maximum number of programming pulses before verifying the program. -0-
Embedded State Machine - During ZPSD813F programming, the
embedded state machine constantly polls the memory cells. When a
cell is fully programmed, the state machine sends a signal to the
tester or PC via the two extra JTAG pins verifying that
programming is complete. The tester then moves to the next memory
cell without waiting for additional, unnecessary programming
pulses.
Address Incrementing - After loading the first 17-bit address and
8-bits of data, the embedded programming algorithm on the
ZPSD813F increments the memory addresses, rather than loading
them. Address incrementing cuts the total time to program from
750 ns per address to only 240 ns per address.
Pipe-lining - Finally, the ZPSD813F JTAG interface has a
two-stage ISP pipeline that additionally doubles serial
programming throughput (while one byte is being programmed, the
next byte is being downloaded.)
This novel 0serial JTAG programming approach substantially cuts the time required to program the flash or EEPROM memory. Radically Simplifies Parallel ISP in MCU-based Systems - Many of the most popular MCU architectures will not allow program space to be written to, making it virtually impossible to do parallel in-system programming. These include the 8031, 8051XA, 80C251, and 68HC11. ZPSD813F devices eliminate this problem with a special on-chip ISP decoding and re-mapping PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user. . The ISP decode PLD handles addressing issues during flash parallel erase/write. At run time, the MCU instructs the ZPSD813F's ISP decode PLD to disable the data addresses and shift program memory addresses to data space. When the flash erase/write is complete, the ISP decode PLD shifts the program addresses back to program space and re-enables the data addresses. Allows Parallel Flash/EEPROM Write/Erase During Operation Several ZPSD813F devices (ZPSD813 F1, ZPSD813F2 and ZPSD813F4) have a second memory array that enables parallel programming of either NVM (Non-Volatile RAM) See NVRAM. array, during system operation. The MCU can operate from either NVM array while the other is being programmed. Most other flash NVM devices, including those with a separate boot block, cannot perform MCU-controlled parallel ISP because there is no program memory from which the MCU can operate during erase/write operations. 3,000 Gates of MCU-Addressable Programmable Logic - ZPSD813F devices have the equivalent of 3,000 gates of WSI's Micro-Cell(TM)-based programmable logic. Micro-Cells are special microcontroller macrocells that provide a direct bus connection between the microcontroller and the PLD flip-flops, eliminating the need to go through the PLD array and saving the equivalent of 1,200 gates of logic usually required to establish the MCU-to-logic connection. The direct access provided by the Micro-Cell architecture saves as many as 30 macrocells and 32 product terms and can cut several weeks from the design cycle. The ZPSD813F's PLD has 24 inputs and 16 output Micro-Cells. This is sufficient programmable logic to implement complex peripheral functions including dual processor interfaces, mail boxes, keypad scanners, timers, counters, interrupt controllers, shift registers and others. Programmable MCU Interface - Using WSI's PSDsoft design tool suite, the ZPSD813F's programmable MCU interface can be configured in less than a minute to operate with most 8- or 16-bit CISC MCUs in muxed or non-muxed mode. PLD Delays and Access Times - The 5-volt ZPSD813F MCU peripheral ICs have access times as low as 90 ns. The Micro-Cell PLD has an address-to-data-out delay of 25 ns. EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. Support - WSI's PSDsoft 5.0 EDA tool suite provides quick menu-driven configuration of the ZPSD813F's programmable MCU interface. The tool's fitting routines automatically optimize the Micro-Cell logic, making full use of product term and MicroCell allocators to fit the design. PSDSOFT also automatically generates the ZPSD813F's programming and control algorithms, including specific memory addresses and pin assignments, for inclusion in the MCU firmware. PSDsoft ensures there is no overlap with logic and memory addresses. The entire DK-800 development kit which includes PSDsoft and a programming cable is priced at only $99. WSI's low cost FlashLink(TM) JTAG programmer for the ZPSD813F allows MCU code or ZPSD813F logic designs to be quickly programmed and tested in the prototype system from a PC parallel port. Packages and Pricing - ZPSD813F devices are available now in production quantities in 52-pin PLDCC and 64-pint TQFP See QFP. packages and are priced as follows in quantities of 25,000 per year: -0-
Main Second
Device CPLD Flash Array Flash Array EEPROM SRAM
ZPSD813F5 3,000 gates 128 Kbytes ---- ----
ZPSD813F4 3,000 gates 128 Kbytes 32 Kbytes ----
ZPSD813F3 3,000 gates 128 Kbytes ---- ---- 2 Kbytes
ZPSD813F2 3,000 gates 128 Kbytes 32 Kbytes ---- 2 Kbytes
ZPSD813F1 3,000 gates 128 Kbytes ---- 32 Kbytes 2 Kbytes
Device Price
ZPSD813F5 $ 5.08
ZPSD813F4 $ 5.95
ZPSD813F3 $ 5.72
ZPSD813F2 $ 6.37
ZPSD813F1 $ 8.89
WSI is the leading supplier of highly integrated programmable solutions for high-speed embedded control designs. Its PSD (tool) PSD - Portable Scheme Debugger. families of single-chip, field-programmable microcontroller peripherals off-load microcontroller functions so that MCUs can operate faster and do more. The power-conserving features of PSD devices can extend system battery life by several hours. The company's family of high performance non-volatile memory products offers densities of 16 Kbit to 1 Megabit with access times as low as 25 ns and 3.3 volt devices with access times as low as 70 ns. WSI is located in Fremont, California. EasyFLASH, PSDsoft and FlashLink are a trademarks of WSI. MagicPRO III is a registered trademark of WSI. Windows is a registered trademark of Microsoft Corporation. ABEL Abel, son of Adam and Eve, in the Bible Abel, in the Bible, son of Adam and Eve, a shepherd, killed by his older brother, Cain; in the Gospel of St. Matthew, mentioned as the first martyr. is a registered trademark of MINC MINC Multilingual Internet Names Consortium MINC Multicast-based Inference of Network-internal Characteristics MINC Military-Industrial Complex MINC Management Interactive Network Connection (USDA) . WSI's World Wide Web site is www.waferscale.com. Note (1): In a 5-volt system with and MCU ALE Frequencyof 4 MHz, with the Turbo Bit turned off, Note (2): Please see Appendix A for a detailed analysis of power consumption. |
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