Ultima Introduces a Physical Design Solution That Uses Clock Skew for Timing Optimization.

NEW ORLEANS--(BUSINESS WIRE)--June, 21, 1999--

Ultima ClockWise(TM) Performs Useful-Skew Clock Tree Synthesis

To Help Designers Rapidly Achieve Timing Closure

Ultima Interconnect Technology, Inc., an EDA technology and tool developer, today announced that it is entering the physical design solutions market and introducing Ultima ClockWise, the first clock synthesis solution that utilizes clock skew to optimize a chip's timing.

Designed to avoid potential timing problems, Ultima ClockWise helps designers to rapidly achieve timing closure without replacing placement and routing tools. The tool seamlessly plugs into the EDA industry's popular design flows and uses formats (LEF/DEF from Cadence, .lib and SDC from Synopsys) provided by Synopsys, Inc. (Nasdaq:SNPS) and Cadence Design Systems, Inc. (NYSE:CDN).

Ultima ClockWise does much more than a good clock design. Traditional physical design tools separate clock design from other design tasks and simply minimize clock skew -- try to achieve zero clock skew. In contrast, Ultima ClockWise combines clock timing with data-path timing and makes clock skew a useful tool to improve the performance and timing robustness of a chip. The useful skew adjusts the effective timing constraints on data-paths. In fact, designers can reduce the number of design iterations and quickly achieve timing closure by focusing on one signal -- the clock.

According to Joe G. Xi, Vice President, Products and Marketing of Ultima, "Ultima has developed Ultima ClockWise through technology partnerships with a number of customers including some of the world's leading IC suppliers. We were very fortunate to have the opportunity to work closely with these companies from the conception of our product."

"Since its founding, Ultima has set its goal to provide integrated physical design and electrical analysis solutions," said Wayne Dai, Ultima's Founder and Board Chairman. "As the shift toward system-on-chip accelerates, we believe the key for physical design lies in global interconnect issues. With the introduction of Ultima ClockWise, we are positioning Ultima as a provider of physical design solutions that solve key global interconnect problems."

Dai added, "At sub 0.25 micron, fixing problems at the verification stage could be too late. We must help designers prevent timing problems from occurring far earlier in the design flow. However, any physical design tool that is not built on top of a proven electrical analysis foundation is unlikely to provide timing closure solutions. This is a great advantage for Ultima as we draw from our expertise in interconnect analysis."

Ultima ClockWise has been adopted and tested by a number of leading semiconductor companies in U.S. and Japan. In designs ranging from three to ten thousand registers and with as many as 20 clock domains, Ultima ClockWise was able to reduce the number of critical paths by 70 to 100 percent (with 100% timing is closed). The improvement in performance and timing robustness was achieved at minimal cost, typically a 10 to 15 percent increase in the number of buffers, and with minimal efforts by designers.

What Others Say About Clock Skew and Timing Optimization

"Zero clock skew has been the reigning dogma since the earliest days of synchronous circuit design," said John P. Fishburn, Distinguished Member of Technical Staff in Research at Lucent Technologies' Bell Labs (Murray Hill, NJ). "But for just as long, designers who 'know their circuit' have increased performance and safety by flouting the dogma. Virtually every synchronous circuit could be improved with useful-skew. What would help designers tremendously is a CAD tool that can analyze an entire circuit and synthesize the useful-skew clock distribution network. Designers who stick with zero skew must keep in mind that their competitors are not constrained to do so."

"We tested ClockWise on one of our highest performance designs," said Andy Le, CAD Manager at Adaptec. "It achieved timing results substantially better than the existing zero-skew clock tools. Without changing placement and routing tools and without using any post-placement optimization tools, ClockWise removed all cycle time violations and race conditions."

In a benchmark done by one of the major ASIC suppliers, Ultima ClockWise was used to improve the performance of a design. The circuit's target performance was 200MHZ. But using an existing zero-skew clock tool in a timing driven design flow, a negative slack of -0.36ns was produced. This means that the circuit could only operate at 187MHZ. Ultima ClockWise produced a positive slack of 0.28ns and the circuit can now run at 212MHZ, a 14% improvement on performance. Furthermore, ClockWise actually used 10% less buffers and no change was required in any of the placement and routing tools.

What's Different

Few will question that clock is the single most important signal in a timing-critical chip. But in the past, people tended not to consider clock design in the context of full-chip timing. Existing design methodologies view clock skew as a problem. Designers strive for zero skew and are unaware that zero skew is really not the optimum way to achieve either the safest or the highest performance clock design. Great resources are wasted as designers work toward achieving perfect zero skew only to get simultaneous switching current that often causes chips to fail.

Recognizing that the true goal for clock design is to meet a chip's timing requirements, the new methodology used with Ultima ClockWise combines clock timing with data-path timing. Ultima ClockWise treats clock skew not as a problem but as a controllable design variable. It now uses clock skew as a useful tool to optimize timing. The optimization brings multiple benefits including: -0-

--   Reducing the number of critical paths to reduce design iterations
     and achieve timing closure.
--   Increasing clock frequency to improve performance.
--   Increasing tolerance to process variations and other intermittent
     noises.
--   Creating a larger tbility of useful skew to increase scalability
 ithm
that handles circuits with tens of thousanechnologies such as highly accurate
cell and
interconnect delay analysis and high-capacity 3D parasitic extraction.

     Price And Availability

     Ultima ClockWise is available immediately. Its price starts at
$120, 000 (USD) for Hewlett-Packard and Sun Microsystems UNIX
workstations.
     The first public showing of Ultima ClockWise is this week at the
1999 Design Automation Conference, booth number 1642, in New Orleans,
Louisiana, USA. The Company is also demonstrating its deep submicron
interconnect analysis and signal integrity verification
solutions-Ultima Nautilus(TM) and Ultima Nautilus-SI(TM).

     About Ultima

     Ultima Interconnect Technology is a technology leader in
interconnect and physical design analysis solutions. The company's
tools and technologies address the tough challenges presented by 0.25
micron and below processes. Ultima's mission is to provide integrated
physical design and electrical analysis solutions and help designers
to close the productivity gap brought by fabrication technologies. The
Company's products are Ultima ClockWise, the useful-skew clock
synthesis solution; Ultima Nautilus-SI, a full-chip signal integrity
verification solution; Ultima Nautilus, a full-chip 3D RC extraction
tool; Ultima PRedator(TM), a parasitic RC reduction tool; and Ultima
Millennium(TM), a full-chip delay analysis solution for timing
sign-off.
     In 1996, Ultima was awarded a contract to develop 3D net
extraction as part of Sematech's Chip Hierarchical Design System
(CHDS). Ultima is a member of Mentor Graphics' (Nasdaq:MENT) OpenDoor
program, Synopsys' (Nasdaq:SNPS) In-Sync and Tap-in programs,
Cadence's (NYSE:CDN) Connections third-party software program, and
Ultima participates in the EDA Consortium's Spine99 interoperability
effort with Synopsys and Cadence (www.spine99.com). Ultima
Interconnect Technology, Inc. headquarters are located at 1139
Karlstad Drive, Sunnyvale, CA 94089, USA, 1-408-734-0600,
Fax: [phone], [e-mail], www.ultimatech.com.

     Contacts for Reader Inquiries

     Ultima Interconnect Technology, Inc., 1139 Karlstad Drive,
Sunnyvale, CA 94089, USA. 408/734-0600, Fax: [phone],
[e-mail], www.ultimatech.com Attn: Kathy Palus

     Notes to editors

     Ultima ClockWise clock skew and design flow graphics available on
request. Gary Smith, Dataquest, has been briefed on this announcement,
[e-mail].
     Ultima ClockWise, Ultima Millennium, Ultima Nautilus, Ultima
Predator and Ultima Useful Skew are trademarks of Ultima Interconnect
Technology, Inc. All other trademarks are the property of their
respective owners.
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Acronyms and definitions:

ASIC: Application Specific IC ASSP: Application Specific Standard Product CHDS: Chip Hierarchical Design System COT: Customer's own tooling DSM: Deep Submicron EDA: Electronic Design Automation IC: Integrated Circuit RC: Resistor Capacitor SoC: System-on-a-Chip