Ubicom Unveils Groundbreaking IP3023 Wireless Network Processor Based on Revolutionary ``MASI'' Architecture.

Business Editors/High-Tech Writers

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--April 15, 2003

Entirely New Architecture Category Results from Nearly Five

Years of Work in Software I/O

Ubicom(TM), Inc., a leading provider of wireless network processor and software platforms, today broke new ground in the wireless network processor market with the announcement of its landmark IP3023(TM) processor. The culmination of nearly five years of work in software I/O, the IP3023 is the first in the IP3000(TM) family of wireless network processors, and has led to the definition of an entirely new microprocessor architecture category, called the Multithreaded Architecture for Software I/O (MASI). Analogous to the way CISC and RISC transformed desktop and high-performance computing, MASI is expected to have a similar impact on the wireless networking market.

"We tasked some of the best minds in the engineering world with developing a new microprocessor designed from the ground up for software I/O and wireless networking," said Bulent Celebi, president and CEO, Ubicom, Inc. "This required an entirely new architectural approach, unlike anything that could be achieved using traditional CISC or RISC techniques. While MASI draws upon many age-old engineering principles, it is the combination of these principles that has enabled us to deliver the industry's first fully optimized wireless network processor."

MASI: A Revolutionary Architecture That Will Transform Wireless Networking

The MASI architecture is designed specifically to enable high-performance execution of software I/O. Software I/O implements all communications and control functions in software, eliminating costly dedicated hardware I/O that can account for as much as 75 percent of a chip's die area. In addition, because software is fundamentally easier to change than hardware, software I/O can be easily adapted and upgraded as applications demand or as standards evolve.

"Wireless networking requires an architecture that is optimized from the ground-up for packet processing -- not one that is encumbered by the features and functions needed for general-purpose computing," said Sanjay Iyer, senior analyst, The Linley Group. "Ubicom's MASI architecture, as implemented in the IP3023 wireless communications processor, employs intelligent simplifications and a radical hardware-software partitioning to deliver a high-performance wireless solution that reaches low cost and power levels unattainable by conventional general-purpose communications processors."

A variety of well-known engineering principles must come together to achieve high-performance software I/O. It is the combination of these techniques that makes MASI truly revolutionary. The architecture is characterized by:

-- Determinism: MASI features deterministic execution, allowing

developers to exactly time a software routine.

-- Multithreading: MASI is a multithreaded architecture that,

when combined with its deterministic nature, allows each

thread to operate independently with no impact from conditions

among threads. As a result, each thread can be seen as a

separate processor. In addition, each thread is programmable,

allowing systems to be easily upgraded in the field as

standards change.

-- Memory-to-memory: MASI requires a memory-to-memory

architecture that enables the processor to move "inputs"

directly to memory and "outputs" directly from memory to the

I/O pins in real time.

-- Bit Manipulation: MASI requires strong bit manipulation

instructions to allow efficient access of individual I/O pins.

IP3023: The Ideal MASI Implementation for High-Performance Wireless Applications

The IP3023 is Ubicom's latest implementation of the MASI architecture, and features a mature second-generation instruction set to make it the performance leader in Ubicom's growing product portfolio. The device builds upon the successes gained with its first wireless network processor, the IP2022(TM), achieving a 10x performance improvement, as well as a number of industry firsts. The IP3023 features:

-- Eight-Way Multithreading: The IP3023 chip features eight-way

deterministic, instruction-level hardware multithreading

enabling it to handle eight different execution threads in its

pipeline simultaneously. This allows it to act as eight

virtual microprocessors, with as many as six threads dedicated

to software I/O functions. In addition, a 64-entry scheduling

table enables the developer to assign a different, flexible

number of MIPS to each hard real time (HRT) thread. Each

thread can have a speed ranging from 0 - 250 MHz, assigned in

3.9 MHz increments.

-- Zero-Cycle Context Switching: A zero-overhead scheduler

enables multithreading that is penalty-free. Not only do

developers get to take advantage of up to eight virtual

processors, but they can also avoid the typical switching

penalties of general-purpose processors.

-- Memory-to-Memory: The IP3023 features a memory-to-memory

architecture that processes data directly in memory using a

single instruction that reads, modifies, and writes the data

in a single cycle. Because packet-processing operations need

only access data once, the use of a single instruction is

significantly more efficient, saving valuable clock cycles and

reducing overall code size. This eliminates the load/store

instructions required by desktop computing architectures, and

found in general-purpose operating systems. As a result, one

instruction in Ubicom's new processor does the work of five

instructions on a comparable platform.

-- Strong Bit Manipulation: The IP3023 features strong bit

manipulation that allows direct access of pins from the CPU

core, and the efficient manipulation of packet headers.

-- Optimized Instruction Set: The IP3023 features an instruction

set designed specifically for wireless networking. As a

result, it uses just 41 instructions, eliminating much of the

overhead associated with traditional approaches and reduces

memory requirements by up to 95 percent. This also eliminates

the use of costly on-chip caches lending to very low latency.

With on-chip memory, the device can achieve 1 gigabyte/second

of memory bandwidth.

-- Deterministic Operating System: The IP3023 is optimized to run

Ubicom's, deterministic operating system, which is structured

so that interrupts can be managed without ever turning them

off.

IP3023: Building on the Successes Achieved with the IP2000 Family

While the IP2000(TM) family processors remain ideal for a variety of wireless networking applications, the IP3000 family delivers the added horsepower needed to implement higher data rate protocols such as 802.11a/g, and to drive high-performance wireless applications like gateways, routers and multiprotocol access points. Ubicom has increased the number of threads supported from two on the IP2022, to eight on the IP3023, allowing the processor to support more software I/O simultaneously. Multithreading also enables zero-cycle context switching, an improvement over the already revolutionary 3-cycle context switching supported on the IP2022. The following table summarizes the key features of the IP3023:

    Feature                         IP3023
    --------------------------      --------------------------
    Threads                         8
    Context Switch                  0 clocks
    Data Path                       32-bit
    Clock Speed                     250 MHz
    Code RAM                        256 kilobytes
    Data RAM                        64 kilobytes
    Process Technology              0.13-micron
    MII Ports                       4
    SerDes Units                    2
    External Memory Controller      SDRAM

Packaging, Pricing and Availability

The IP3023 will be housed in a 208-pin plastic quad flat package (PQFP). Ubicom expects to sample the device in Q22003, with production slated for 2H2003. The IP3023 will sell for $12 in 100,000-unit quantities per month. Please visit Ubicom's Web site at www.ubicom.com for more information.

About Ubicom, Inc.

Ubicom, Inc. develops and markets wireless network processor and software platforms that enable all electronic devices to be connected to each other -- securely, cost-effectively and transparently. With headquarters in Mountain View, California, Ubicom also has offices in Southern California, as well as Belgium, Taiwan and Hong Kong. For more information, visit www.ubicom.com.

Editors' Notes:

-- A photo, quote sheet and analyst reference sheet on the IP3023

are available. Please call Joany Draeger, Tanis

Communications, 650/365-3395 or e-mail [e-mail].

Ubicom, IP2000, IP2022, IP3000 and IP3023 are trademarks of Ubicom, Inc. All other trademarks are the property of their respective holders.