Printer Friendly
The Free Library
14,800,529 articles and books
Member login
User name  
Password 
 
Join us Forgot password?

UMC Expands Support for Mentor Graphics' Calibre YieldAnalyzer to Deliver Production Proven DFM Flow.


WILSONVILLE, Ore. -- Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create.  Corporation (Nasdaq:MENT) today announced that UMC UMC United Methodist Church
UMC United Microelectronics Corporation
UMC University Medical Center
UMC United Microelectronics Corp (Republic of China)
UMC University of Missouri-Columbia
 has expanded its support for the Calibre[R] nm Platform with Calibre YieldAnalyzer[TM] for all major design flows for its 90 nanometer (nm) and 65nm processes. Mentor and UMC have worked collaboratively to introduce Design for Manufacturing (DFM DFM Design for Manufacturing (newsletter)
DFM Design for Manufacturability
DFM Dubai Financial Market
DFM Delphi Form (computer filename extension)
DFM Distinguished Flying Medal
DFM Diesel Fuel Marine
) capabilities that give designers highly valuable information to guide physical design improvements that can increase production yields.

As volume IC production moves to sub-100nm, manufacturing costs increase dramatically and yield is increasingly sensitive to both random and systematic defects and process variations. Calibre YieldAnalyzer can mitigate one source of yield loss by performing critical area analysis (CAA Caa

See CCC.
), providing information about how random process defects, such as unwanted particles, result in layout pattern shorts and opens that reduce yield. Designers can use CAA information to modify layouts to reduce the probability of incurring these failures in production.

The DFM collaboration between Mentor Graphics and UMC started in 2005 with the creation of production decks to enable Mentor's Calibre YieldEnhancer[TM] for UMC's 180nm through 65nm processes. YieldEnhancer reduces systematic defects with a variety of pattern enhancements, such as inserting redundant "Vias" and other techniques to improve as-built circuit integrity. YieldEnhancer production decks, as well as the new silicon verified decks for Calibre YieldAnalyzer users, are available upon request through UMC customer representatives.

"Our long-term relationship makes Mentor Graphics a natural choice as an ongoing EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  partner for CAA," said Patrick Lin, Chief SoC Architect, System and Architecture Support at UMC. "We have found that the Calibre YieldAnalyzer tool produces results with excellent correlation to our internal data standard. This work complements our existing Calibre YieldEnhancer Via-doubling decks that also provide excellent coverage and outstanding throughput performance for layout enhancement. We believe our support for Calibre's DFM tools provides a valuable advantage for our mutual customers."

"YieldAnalyzer and YieldEnhancer are just two components of the expanding Calibre nm Platform first introduced a year ago with nmDRC," said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. "Building on our powerful, production-proven Hyperscaling architecture, we are delivering the broadest, most accurate, and best performing DFM solutions in the industry. Because the Calibre platform is built on standard open database interfaces, it brings production proven DFM capabilities to UMC customers, independent of the design creation environment they use."

About the Calibre DFM Platform

Mentor Graphics offers a full range of DFM analysis and enhancement solutions for random, systematic, and parametric process issues affecting production yield. Calibre nmDRC is the industry standard for physical verification Physical verification

A procedure auditors use to ensure that inventory recorded in the book is correct by actually checking out the physical inventory.
, with Hyperscaling technology that supports simultaneous execution on up to 100 CPUs for dramatically improved runtimes. Calibre LVS LVS Linux Virtual Server
LVS Live Vaccine Strain
LVS Las Vegas, New Mexico (Airport Code)
LVS Low Voltage Switchgear
LVS Logistical Vehicle System
LVS Laser Vibration Sensor
LVS Logistics Vehicle System
 is the market-leading layout vs. schematic physical verification tool, which extracts the most advanced device properties from state-of-the-art device models. Calibre xRC[TM] and xL parasitic extraction tools deliver accurate interconnect models, and their hierarchical structure See hierarchical.  provides breakthrough performance even for very large designs. Calibre YieldAnalyzer combines critical area analysis (CAA) and critical feature analysis (CFA (Computer Fraud and Abuse Act of 1986) Signed into law in 1986, the CFA was a significant step forward in criminalizing unauthorized access to computer systems and networks. The Act applies to "federal interest computers" that include any system used by the U.S. ) into a single integrated solution. YieldEnhancer recommends and performs specific layout modifications, such as via doubling, via extensions and enclosures, to increase production yield. Calibre LFD LFD Laufend (German: current)
LFD Laboratory for Fluorescence Dynamics (University of Illinois at Urbana-Champaign)
LFD Left for Dead (band) 
[TM] addresses issues related to lithographic lith·o·graph  
n.
A print produced by lithography.

tr.v. lith·o·graphed, lith·o·graph·ing, lith·o·graphs
To produce by lithography.
 process effects by modeling the effects of process variability on both devices and interconnects, and identifying layout "hot spots hot spots

acute moist dermatitis.
" that can be improved to ensure higher yield. Calibre nmOPC, OPCpro[TM], OPCverify[TM] and other related tools provide a complete solution for layout resolution enhancement and mask data preparation Mask data preparation is the step that translates an intended set of polygons on an integrated circuit layout into a form that can be physically written by the photomask writer. . Dense simulation, contour-based design intent constraints, Cell Broadband Engine compatibility, and other innovations allow the Calibre environment to deliver unprecedented accuracy and performance at the lowest cost of ownership.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,250 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: www.mentor.com.

Mentor Graphics and Calibre are registered trademarks and Calibre LFD, YieldEnhancer, YieldAnalyzer, Calibre xRC, Calibre OPCpro and Calibre OPCverify are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
COPYRIGHT 2007 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2007, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

 Reader Opinion

Title:

Comment:



 

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:May 15, 2007
Words:728
Previous Article:SeeSaw Networks Co-Founder Shares New Media Measurement Best Practices at 2007 Digital Signage Expo.
Next Article:Tao Minerals Enters Negotiations to Acquire Producing Gold Property "El Colmillo".
Topics:



Related Articles
Mentor Graphics and UMC Deliver IC Design Kits Through Expanded Partnership Design Kit Support is an Important Factor in RF and AMS Design.
Mentor Graphics Calibre ``Golden'' Rule Files Available for 90nm Technology Process at UMC.
UMC Validates the Mentor Graphics Calibre xRC Parasitic Extraction Solution for 90nm Process Technology.
Mentor Graphics Announces Calibre Encryption Technology Adopted by IBM.
Mentor Graphics Unveils New Calibre Litho-Friendly Design Product, Bringing Process Variability Data into the Design Flow.
Mentor Graphics Calibre Tools Strengthen DFM Flow for IBM/Chartered/Samsung 65-nm Common Platform Technology.(Company overview)
Mentor Graphics Calibre Platform Provides Integrated DFM Flow for TSMC 65nm Technologies.
STARC Standardizes on Calibre YieldAnalyzer as Reference Tool in DFM Flow for Critical Area Extraction.
Mentor enables institute to offer educational opportunities for EEs.(HEAD OF THE CLASS)
Mentor Graphics' DFM Solution Qualified by Common Platform Technology Alliance for 45nm and 65nm.

Terms of use | Copyright © 2010 Farlex, Inc. | Feedback | For webmasters | Submit articles