Tru-Si Technologies Gives New Life to Moore's Law.

SUNNYVALE, Calif.--(BUSINESS WIRE)--Nov. 11, 1999--

Revolutionary Technology Resolves the Problems of Chip-to-Chip

Vertical Interconnection -- First by Stacking Wafers

and Then Dicing Them

Tru-Si Technologies, Inc. (Tru-Si), the world leader in atmospheric downstream plasma (ADP) processing for vertical miniaturization solutions, today announced an exciting breakthrough in the continuous quest to overcome the challenges that threaten Moore's Law. Utilizing its already-successful atmospheric downstream plasma (ADP) etching process, the company has discovered a unique, yet remarkably simple method of successfully stacking multiple chips by stacking wafers containing different circuit functions such as memory, logic, analog and digital, etc. This revolutionary technology, which maintains the economies of scale inherent in processing whole wafers, provides thru-silicon vertical interconnections between the front and back sides of a wafer in a manner similar to that of through-holes in printed circuit boards. The result is a new concept in the ultimate three-dimensional stacked wafer level packaging (S-WLP) and a new, three-dimensional Moore's Law.

According to semiconductor technology roadmaps, Moore's Law, which states that approximately every two years, the number of transistors per chip area doubles, is confronting its most serious front-end challenge ever. Experts are forced to admit that with area geometries continuing to shrink, it may not be possible to reduce feature size to the point where tens of atoms determine the device characteristics. As a result, device area shrink efforts will slow down progress and the doubling timescale of Moore's Law could easily increase to well beyond two years within a few device "generations."

"We are extremely excited to be giving new life to Moore's Law by blazing this trail toward chip-to-chip vertical interconnection. The goal is to create a stack of ten integrated circuit (IC) wafers, which is equal to the size of a current single wafer," said Tru-Si's Chief Executive Officer, Dr. Sergey Savastiouk. "By using our ADP etching system, the company's customers have already embarked on the first step in vertical miniaturization: damage-free thinning (DFT) of wafers down to 50 microns in one highly-reliable, high-yield step. Now, we have discovered that this same technology can also be used to enable the second step in the vertical miniaturization and integration process -- stacking chips by stacking wafers (S-WLP) in a cost-efficient, simple manner, which virtually eliminates the problems associated with chip-to-chip interconnections. Diced stacked wafer level packages (S-WLP) result in stacked chip-scale packages (S-CSP) which is an emerging trend favored by major chip making companies for the production of stacked memory modules(a). The revolutionary result allows for the introduction of a new three-dimensional Moore's Law -- doubling of IC density approximately every two years -- not on the surface of the silicon area as the current law states, but in three-dimensional stacked silicon."

So far, the primary technical obstacle to mass production of high-density, vertically integrated modules is the challenge of forming die interconnections within a vertical chip stack. The flip-chip concept does not allow for interconnection of more than two chips. Wire bonding methods are limited to the number of chips that can be efficiently stacked and they require manufacturers to link chips over edges. The formation of over-edge chip interconnections, however, is not only lengthy and barely automated, it is also extremely cost-inefficient for high-volume production, and not applicable for wafer level packaging. Lengthy chip-to-chip interconnections are generally outside of the silicon environment and present a performance bottleneck, in spite of the performance superiority of the separated chips. As a result, designers are forced to dedicate significant amounts of silicon and board space for "pumping" signals from one chip to another. Since chip characteristics generally outperform interconnection characteristics, the latter represents the most critical back-end challenge.

Unless the miniaturization drive shifts its focus toward vertical miniaturization and integration, further investment in reducing feature size will generate diminishing return. Tru-Si's ADP technology offers a potential solution by deftly circumventing the chip-to-chip interconnection bottleneck with a simple method of creating vertically stacked chips using vertically stacked, multiple wafers containing different functions.

Using its ADP process as the supporting equipment, Tru-Si creates thru-silicon wafer-to-wafer interconnections in a simple set of steps. The first step is to form deep isolated metal vias (50 to 150-microns deep) on the front side of a wafer that are connected to appropriate layers of circuitry. The second step is to apply the ADP damage-free thinning (DFT) technology to selectively remove silicon from the back side of the wafer, carefully exposing the deep thru-silicon vias without any mask. The natural etch selectivity of ADP enhances the simplicity of this process and ensures the clean, highly-reliable formation of rigid thru-silicon contacts (as high as 25 to 50 microns) on the back side of a wafer. These back-side contacts offer flip-chip-type performance characteristics and can be directly bonded to another wafer or substrate without an extra bumping process.

Tru-Si will be unveiling the latest results of its vertical miniaturization and yield enhancement solutions at the MEPTEC Symposium at the Hyatt San Jose, San Jose, November 16, and at SEMICON Japan, Dec. 1-3 at booth number 2-A001. A presentation outlining Tru-Si's vertical miniaturization and yield enhancement solutions will be available on Tru-Si's website at http://www.trusi.com

(a)Semiconductor Business News, July 6, 1999

About Tru-Si Technologies

Tru-Si was founded in 1996 with a mission to focus on vertical miniaturization and yield enhancement solutions, and is the world leader in atmospheric downstream plasma (ADP) semiconductor process equipment with a mission to focus on vertical miniaturization and yield enhancement solutions. ADP processes are applied for both front and back end applications such as damage free isotropic etching and film stripping as well as damage free thinning down to 50 microns. This is accomplished without the need for expensive frontside wafer protection or the use of hazardous chemicals required in wet etching and chemical mechanical planarization. Tru-Si's systems also incorporate the company's proprietary No-Touch wafer handling technologies to enable the manufacture of ultra-thin semiconductors for high-density and high-performance chip markets including smart cards, hand-held devices and other applications. Tru-Si's revolutionary thru-silicon solution resolves the problems of chip-to-chip vertical interconnection by stacking wafers. System-on-a-stack (SOS) concept enables the new system-on-a-chip (SOC) architectures. Tru-Si is headquartered in Sunnyvale, Calif. For more information on Tru-Si, visit the company's web page online at http:// www.trusi.com