TransEDA Announces Simulation Edge Suite for Faster Design Verification At 50 Percent Savings.Business/High Tech Editors LOS GATOS, Calif.--(BUSINESS WIRE)--Aug. 20, 2001 Simulation Edge Verification Suite Features Ready-to-Use, Integrated Solution at One Low Price TransEDA(R), the leader in ready-to-use verification solutions, today announced its Simulation Edge(TM) verification suite, offering FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. , ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. and SoC designers faster time-to-market at half the price, with TransEDA's integrated design verification solutions. The Simulation Edge suite is ready-to-use with existing simulation environments and verification flows to dramatically speed the functional verification process. The suite offers a configurable HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. checker, coverage analysis, and test suite analysis in one bundle with a common interface. At up to 50 percent off the regular list price for the combined set of tools, designers can speed time-to-market while keeping tool costs and vendor count to the absolute minimum. "TransEDA's Simulation Edge suite is an integrated verification solution at a great bundled price," said Tom Borgstrom, vice president of marketing at TransEDA. "The Simulation Edge suite can be used by all RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designers to achieve a time-to-market edge by reducing the simulation iterations needed for functional closure. It is also painless to install, integrate, learn and use so designers can get up and running quickly. Add to this the time saved by working with a single vendor for a variety of verification tools, and designers really get an edge." Simulation Edge Suite - An Integrated, Ready-to-Use Solution The Simulation Edge verification suite offers a powerful combination of three best-in-class verification tools that work seamlessly together and are easily integrated into existing RTL design flows: -- VN-Check(TM) Configurable HDL Checker: With built-in rule sets and easily configured rules, VN-Check identifies bugs before simulation when it is easiest to fix them, cutting time and effort spent on simulation. -- VN-Cover(TM) Coverage Analysis: The leading Verilog, VHDL and dual-language coverage solution, VN-Cover enables designers to identify and focus test development effort on the areas of a design that have yet to be fully simulated, slashing the number of simulation iterations required. -- VN-Optimize(TM) Test Suite Analysis: Working seamlessly with VN-Cover coverage results, VN-Optimize analyzes test sets from large regression suites and identifies the smallest set of tests that will meet verification goals, dramatically reducing the time and resource requirements for regression testing. Verification Navigator(TM) The tools in the Simulation Edge suite are part of TransEDA's Verification Navigator integrated design verification environment. Verification Navigator provides tools that enable IC designers to manage the verification process and shorten verification time. In addition to VN-Check, VN-Cover and VN-Optimize, Verification Navigator includes VN-Control(TM) Application Specific Test Automation. Verification Navigator supports all leading Verilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and dual-language simulators and is available on the Solaris, HPUX HPUX Hewlett-Packard Unix , AIX (Advanced Interactive eXecutive) IBM's Unix-based operating system which runs on its Intellistation workstations and pSeries, p5, iSeries and i5 server families. , Linux, Windows NT, and Windows 2000 platforms. Pricing and Availability The Simulation Edge verification suite, featuring VN-Check, VN-Cover, and VN-Optimize, is available now through December 31, 2001, in Verilog, VHDL, language neutral, and dual language configurations. Pricing starts at $30,000 for a perpetual license, a 50 percent savings off list price for the combined tools. Subscription-based pricing is also available. For more information on the Simulation Edge suite, visit www.transeda.com/simulationedge. About TransEDA TransEDA PLC (symbol TRA on the London Stock Exchange London Stock Exchange London marketplace for securities. It was formed in 1773 by a group of stockbrokers who had been doing business informally in local coffeehouses. ) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (hardware) field-programmable gate array - (FPGA) A gate array where the logic network can be programmed into the device after its manufacture. An FPGA consists of an array of logic elements, either gates or lookup table RAMs, flip-flops and programmable interconnect wiring. (FPGA), application-specific integrated circuit (hardware) Application-Specific Integrated Circuit - (ASIC) An integrated circuit designed to perform a particular function by defining the interconnection of a set of basic circuit building blocks drawn from a library provided by the circuit manufacturer. (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models for advanced microprocessors and bus interfaces. TransEDA's design verification software performs application-specific test automation, configurable HDL checking, functional, finite state machine See state machine. (mathematics, algorithm, theory) Finite State Machine - (FSM or "Finite State Automaton", "transducer") An abstract machine consisting of a set of states (including the initial state), a set of input events, a set of output events, and a state transition (FSM) and code coverage analysis, and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the world's top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 985 University Avenue, Los Gatos, California “Los Gatos” redirects here. For the Argentine rock band, see Los Gatos (band). Los Gatos is an incorporated town in Santa Clara County, California, United States. The population was 28,592 at the 2000 census. 95032 U.S.A., telephone 408/335-1300, fax 408/335-1319, email info@transeda.com. Note: TransEDA is a registered trademark and Verification Navigator, VN-Check, VN-Cover, VN-Optimize, and Simulation Edge are trademarks of TransEDA. All other trademarks are properties of their respective holders. |
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