Tower Semiconductor Releases 0.18 and 0.35 Micron Process Design Kits.

Business Editors/High-Tech Writers

MIGDAL HAEMEK, Israel & SAN JOSE, Calif.--(BUSINESS WIRE)--June 24, 2003

Cadence-Developed PDKs Reduce Risk and Simplify the Silicon

Design Process for Tower's Customers

Tower Semiconductor Ltd. (Nasdaq:TSEM), an independent pure-play wafer manufacturer, and Cadence Design Systems Inc. (NYSE:CDN), today announced the immediate availability of the new Tower TSL018 and TSL035 foundry-level Process Design Kits (PDKs) developed by Cadence Design Systems. The new PDKs eliminate the need for Tower customers to create their own "views" of the Tower technologies in their design environments, thereby reducing design time and risk. Through this development, Tower and Cadence are enabling a key component of the silicon design chain for their mutual customers.

"The ability to support custom design methodologies with silicon-validated process design kits is a strong benefit to companies working with these complex designs," said Sergio Kusevitzky, vice president of IP and design services, Tower Semiconductor. "Cadence's track record of expertise and commitment to customer support has proved to be the most effective choice for our customers."

The PDKs include a device and symbol library, technology file, physical verification decks, and design-rule-correct parameterized cells (P-cells) to automate device layout. The PDKs are compatible with the Cadence Spectre(R) models provided by Tower Semiconductor and are tailored for use in the Cadence RF/analog mixed-signal design solution consisting of AMS Designer, Composer, Analog Design Environment, Spectre/Spectre-RF, Virtuoso(R) Layout Editor and XL, Custom Router and the Assura(TM)/Diva(R) physical verification suites.

"The development work with Tower Semiconductor demonstrates our on-going commitment to the foundry market and the silicon design chain. The PDKs we have supplied provide a silicon foundation for Tower customers to design in the Tower process," said Guillaume d'Eyssautier, senior vice president and general manager, Europe, Cadence Design Systems.

About Tower Semiconductor Ltd.

Tower Semiconductor Ltd. is a pure-play independent wafer foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.18 microns; it also provides complementary manufacturing services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35 microns and can produce up to 20,000 150mm wafers per month. Fab 2 features 0.18-micron and below process technologies, including foundry-standard technology, and will offer full production capacity of 33,000 200mm wafers per month. The Tower Web site is located at www.towersemi.com.

About Cadence

Cadence is the world's leader in electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif, and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks and Virtuoso Custom Design, Virtuoso-XL and Cadence Chip Assembly Router are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.