Timing driven floor planning: how to minimize interconnect delays, without adding routing time. (Interconnect Strategies).

MANY PCBS ACHIEVE their highest levels of performance when interconnect delay is minimized. Floor planning of printed circuits is strongly influenced by the need to satisfy timing budgets for the circuits present with full consideration of PCB interconnect delay. Floor planning is important as today's interconnect modeling and simulation technologies permit timing budget excesses to be identified in placement solutions long before the schedule and budget are spent on detailed routing tasks.

Interconnect delay estimates based on Manhattan routing distances between nodes are used in developing PCB floor plan solutions. Manhattan distances are good for predicting delay in unrouted topologies because PCB signal routing layers are biased primarily in horizontal and vertical directions. Under normal circumstances, signal routing will have to respect the layer bias direction or overall routing density will suffer. In my experience it is easier to add delay beyond Manhattan distances than to achieve less than Manhattan distances for large numbers of conductors in dense PCBs. Sometimes just knowing where an absolutely direct routing path is required to meet timing will help keep the routing solution on track (FIGURE 1).

[FIGURE 1 OMITTED]

The floor planning of a simple parallel power PC-based signal processor card will demonstrate this strategy. This particular circuit uses three MP750 power PC microprocessors, each with its own 1MB external L2 cache static burst RAM and local processor power supply circuits. Each microprocessor subcircuit uses a dedicated memory controller to interface to its 1GB block of PC133 SDRAM main memory. All three of the processor subcircuits are linked by a 66 MHz local PCI bus to a pair of PCI bridge devices, one for the local on-card disk and LAN I/O, and one for the 33 MHz system level PCI bus that spans multiple card slots in the chassis

Floor planning should begin with the most challenging subcircuit timing condition, in this case a 200-plus MHz L2 bus interface between the MP750 microprocessor and an array of two 512 K static rams. Many orientations and relative positions were tried and delay predictions made. In the end, the only solution that could meet interconnect delay budget specifications was to stack the static RAM PLCC packages on their primary and secondary sides directly adjacent to the L2 interface side of the processor BGA package, and optimize all data and address signal assignments on the memories to absolutely minimize interconnect delay.

The next most-challenging microprocessor subcircuit timing goal was the memory controller to the main memory PC133 SDRAM's bus. The memory was packaged in two PC133 right-angle slots to meet height restrictions within the narrow card slots. Manhattan distances between the outermost PC133 DIMM slot pins and the memory interface side of the memory controller BGA required the memory controller to be centered directly adjacent at right angles to the first DIMM slot 0. The second PC133 right-angle memory socket was changed to a reversed pin assignment version, effectively flipping the DIMM to permit a fast, direct path for signals between slot 0 and slot 1.

Last but not least, the 133 MHz microprocessor front-side bus to the memory controller was floor-planned, thus uncovering the need for dozens of additional series terminations. Even with the additional delay consumed by the longer interconnects and chip resistor arrays, timing was met with extra margin when the memory controller was placed directly adjacent to the front-side bus side of the MP750 processor (FIGURE 2).

[FIGURE 2 OMITTED]

Once a solution is found for each of the repeated subcircuits, they can then be floor-planned at the board level. In this case, care was taken to reuse the placement and routing solutions where symmetry existed, leveraging circuit symmetry to reduce development time. For the signal processor card, this meant arranging each of the three microprocessor subcircuits so as to leave them intact while attempting to satisfy the interconnect timing for the local 66 MHz PCI bus between the two remaining PCI bridge devices also tied to this bus.

A straight, direct routing path configuration for the 66 MHz local PCI bus was found by orienting one of the T-shaped processor subcircuit blocks 180[degrees] from the others. This type of DIMM connector is wider than the column formed by the processor, memory controller and stacked L2 cache packages, leaving two "holes" in the final configuration. The two BGA-packaged PCI bridge devices fit nicely in these two open holes and resulted in an almost straight line 66 MHz PCI bus between all five PCI devices, with little or no wasted space. This configuration is also respectful of the large circular heatsinks on each MP750. The system PCI bus bridge device was positioned in the uppermost location to minimize the electrical length between it and the backplane I/O connector (FIGURE 3). Simulation confirmed that the stub length for the worst-case multidrop system PCI bus signal satisfied 33 MHz PCI settling time specifications.

[FIGURE 3 OMITTED]

BERNARD VOSS is principal interconnect specialist at SiQual Inc. (siqual.com), a consulting group. He can be reached at [e-mail].