Timing analysis principles for digital PCBs, Part 3: on source synchronous designs: applications and timing characteristics.

FOR SUCCESSFUL high-speed bus design, it is important to understand the timing analysis methodologies (at system level) applicable to various signaling schemes. It has been justly stated (13): "Ninety percent of signal integrity problems are timing problems."

Part 2 (PCD&M, June 2006) of this series treated common-clock timing concepts. This part is devoted to source synchronous design offering higher frequency/speed capabilities. Depicted by FIGURE 9, a strobe (clock) is transmitted from driver IC instead of a separate clock chip. Here DQ, DQS and BCLK represent data, strobe and bus clock respectively. First, a DQ bit is transmitted and a short delay later a DQS is sent to latch the data into the receiver IC.

[FIGURE 9 OMITTED]

The timing path initiates at the driver's flip-flop and ends at the receiver's flip-flop. DQS serves as clock input for the receiver's flip-flop. The driver transmits DQS and DQ with a defined phase relationship. Normally, DQS is phase shifted by half cycle from DQ signal. This shifting is sometimes achieved in the receiver. Frequently (but not always), there is one (or two) strobe(s) per byte of data signals. A central clock is not essential for controlling the driver/receiver signal flow.

The setup and hold equations for a source synchronous interface are defined in TABLE 2. To ensure proper source synchronous operation, the strobe transmission must be timed to meet setup and hold requirements of receiver (latch). FIGURE 10 presents the source synchronous setup/bold timing diagrams.

[FIGURE 10 OMITTED]

One source synchronous example is the DDR (dual data rate) memory bus, where data are sampled on both the rising and falling edges of the strobe. DDR is an excellent choice for high-speed interconnects (14) as the clock bandwidth is halved for a given data rate. The DDR 1 (Double Data Rate, version 1) can operate (1-5) at 2.5 V (typical) and data rates approaching 400 Mb/s. DDR-2 can function at 1.8 V (nominal) and up to 800 Mb/s. FIGURE 11 exemplifies a DDR-1 topology suitable for DQ or DQS signals.

[FIGURE 11 OMITTED]

It is advantageous for the strobe and data topologies to be identical to minimize skew (6) and preserve DQ-DQS phase relationship. The traces can then be quite long limited only by losses, latencies, etc.

The driver/receiver buffer strengths are defined in Figure 11. The typical Z0 and Tpd (reciprocal of velocity) values for each line segment (TL1, TL2, TL3, TL4) are also given. The SDRAMs (which receive during write and drive during read cycles) are on the DIMM modules, which plug into J1 and J2. As explained in Part 2, it is frequently insufficient to consider only the typical corner; the fast and slow cases need to be also analyzed. Let us outline the combination of parameters involved for fast, nominal and slow corner simulations.

Fast Corner Driver / Receiver: strong, Z0 =55 [ohm], Pd = 1.8 ns/ft (fastest velocity), Rs = 11.88 [ohm] Rp = 22.22 [ohm]

Typ Corner: Driver / Receiver: Nominal, Z0 = 50 [ohm], Pd = 2.0 ns/ft, Rs = 12, Rp = 22.

Slow Corner: Driver / Receiver: weak, Z0 = 45 [ohm], Pd = 2.2 ns/ft (slowest velocity), Rs = 12.12 [ohm], Rp = 21.78 [ohm]

The package model (Pkg_u1) may be lumped (consisting of R pkg, C_pkg, L_pkg) as in FIGURE 7 (Part 2). However, at higher speeds (fast rise times) it is preferable to use a distributed model represented by a piece of transmission line with Z0 = sqrt(L_pkg / C_pkg) and delay TD = sqrt(L_pkg * C_pkg), or S-parameter model (well suited for GHz speed designs).

When using a lumped package model, the largest C_pkg (provides highest loading) is applied in slow corner simulations. When utilizing a distributed package model, the smallest Z0 and longest TD are employed for slow corner runs. The opposite applies to fast corner simulations. Also, S-parameter package models can be generated based on the longest, nominal or shortest IC's package traces; and thereby designed optimal for slow, typical or fast corner analyses.

Note that for fast corner the smallest Rs and largest Rp (as dictated by each resistors' nominal value and tolerance) are utilized. The opposite is valid for slow corner. Furthermore, for fast and slow corners, the rising and falling flight time measurements are conducted at receiver's Vinh and Vinl (input logic "high" and "low" DC voltages) rather than at mid-point of the rising/falling edges, shown in typical analysis of FIGURE 5b (Part 1).

One reason that source synchronous is advantageous over common-clock bus is that its performance depends on relative, rather than absolute delays (however, the receivers' setup and hold timing requirements must still be fulfilled). In practical systems, smaller delay differences between signals can be achieved as compared to absolute delays. Subsequently, source synchronous signaling permits longer traces and superior performance.

At very fast edge rates, effects due to reflection (overshoot, ringback, etc.) and crosstalk can adversely affect timing; hence, special measures may be needed for margin improvement. DDR-2 can operate faster than DDR-1 (reaching 800 Mb/s) and includes ODT (on die termination) feature. ODT is a dynamic termination incorporated into the SDRAM and memory controller, and can be enabled or disabled depending on write/read modes and addressing conditions (16). DDR-2 designs can also demand slew rate derating (16) (an advanced concept for timing enhancement).

At GHz frequencies, multi-drop buses become prohibitive and topology of choice is point-to-point (as in PCI Express serial links) avoiding stubs.

Eye diagrams provide a preferred means for timing analysis of high-speed differential serial links (with embedded clocks). Eye diagrams can be also applied (6) for setup/hold determination of source synchronous signals, centering the clock transitions in the middle of the data eye (13) and for deriving timing equations.

ACKNOWLEDGMENTS

Special thanks to Peter Arnold, Richard Kuo, Clement Yuen and Dean Gonzales for insightful discussions.

REFERENCES

(13.) Jim Peterson, "Timing Numbers from ICX-What Do We Do With Them?" Mentor Graphics International User Conference, May 2-5, 2006.

(14.) Brian Young, Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages, Prentice Hall, 2000, p. 121.

(15.) Lee W. Ritchey, Right the First Time: A Practical Handbook on High Speed PCB and System Design, vol. 1, Speeding Edge, 2003, p. 122.

(16.) Steve Mckinney, "Successful DDR2 Design" Memory Interfaces Solution Guide, March 2006, pp. 9-13.

ABE (ABBAS) RIAZI is a senior staff electronic design scientist with ServerWorks (a Broadcom company) (server works.com); [e-mail].

TABLE 2. Timing formulas and parameters for a source synchronous bus.

TSu_mrg = [(Tco_dqs,min - Tco_dq,max) + (Tflt_dqs,min - Tflt_dq,max) +
Tdly - Tsu,min] EQ. 3

Thld_mrg = [(Tco_dq,min - Tco_dqs,max) + (Tflt_dq,min - Tflt_dqs,max)
+ Tdly - Thld,min] EQ. 4

With timing parameters as defined below:

Tsu_mrg = Setup timing margin. Thld_mrg = Hold timing margin.

Tee_dq,max = Driver's data output valid delay (max).
Tco_dq,min = Driver's data output valid delay (min).

Tco_dqs,max = Clock-to-output delay of strobe flip-flop (max).
Tco_dqs,min = Clock-to-output delay of strobe flip-flop (min).

Tsu,min = Receiver's input setup requirement (min).
Thld,min = Receiver's input hold requirement (min).
Tdly = Delay between data and strobe clocking.

Tflt_dq,max = Data signal   Tflt_dqs,max = Strobe signal
  flight time (max).          flight time (max).

Tflt_dq,min = Data signal   Tflt_dqs, min = Strobe signal
  flight time (min).          flight time (min).