Timing analysis principles for digital PCBs, Part 2: a look at common-clock bus timing concepts.

WE DISCUSSED TIMING analysis principles in Part 1 of this column (See Interconnect Strategies, April 2006 PCD&M). The central focus of Part 2 will be the common-clock timing scheme. In this approach (FIGURE 6), the bus driver and receiver ICs share the same clock. (6)

[FIGURE 6 OMITTED]

The setup and hold equations for a common-clock interface are defined by TABLE 1.

It is assumed that effects due to crystal frequency variation (typically 100 ppm or less) of the clock generator on Tcyc is negligible. Implied by Tsu,min and Thld,min is that the receiver's setup and hold are usually minimum timing requirements with no associated maximums Tsu,max or Thld,max.

In one clock cycle, several events must occur. The clock period must be budgeted to various operations (7), such as gate switching, signal propagation times, etc. In order for data to be properly latched in, the receiver's setup and hold requirements must not be violated.

An example of a common-clock bus is provided by PCI-X address/data lines. The parameters for setup and hold times are obtainable from Tables 9-11 and 9-12 of PCI-X bus specifications. (8)

For 133 MHz operation, the setup margin parameters include: Tco_dq,max = 3.8 ns, Tclk_skw, max = 0.5 ns (this includes Tjtr), Tsu,min = 1.2 ns, Tcyc = 7.5 ns.

Utilizing Equation 1 of Table 1 yields:

Tsu_mrg = 2.0 ns - Tfltdq,max.

Subsequently, to produce a non-negative setup margin, the flight times should not exceed 2.0 ns.

Also, the hold margin parameters (8) for 133 MHZ PCI-X are:

Tco_dq,min = 0.7ns,

Tclk_skw, max= 0.5ns, Thld,min = 0.5 ns.

From Equation 2 of Table 1:

Thld_mrg = -0.3 + Tflt_dq

This implies that the flight time should be larger than 0.3 ns to avoid hold timing violations. The PCI-X example indicates that bus specifications can be also a good source for timing parameters (and test loads), in addition to the AC section of device data sheets. See Part 1 of this column.

Timing specs furnished by manufacturer data sheets are based on test loads that usually differ from system interconnect loading. Therefore, propagation (or flight) times ascertained through system simulations require certain adjustments before insertion in timing margin computations.

It is necessary to simulate using the reference load in addition to system loading (9), as implied by FIGURE 7. This can eliminate the double-counting portion of buffer delay (3), compensate for system loading effects and produce accurate timing data.

[FIGURE 7 OMITTED]

In FIGURE 7a, Cref and Ref belong to a test load used by semiconductor vendors when specifying propagation delay (10) and/or the output switching time of the device. Vref is the timing specification test load voltage.

In FIGURE 7b, R_pkgl, L_Pkg1 and C_pkg represent the packaging resistance, inductance and capacitance (10) of the driver pin. Similarly, R_pkg2, L_pkg2, and C_pkg2 define package parasitics of receiver pin.

In Part 1 (FIGURE 5a), the driver was modeled as a pulse source in series with a resistor (representing driver output impedance), and the receiver was modeled as a capacitor.

[FIGURE 5 OMITTED]

Figure 7 reveals that to produce more accurate simulations, the actual buffer models should be utilized for driver and receiver devices and the package parasitic elements need to be accounted for. Furthermore, simulation of Figure 5 considered only a typical corner.

More complete data can be produced by also analyzing the fast and slow corners (best and worst cases) in order to verify the design under a full range of manufacturing processes. This necessitates varying the various PCB and buffer modeling parameters such as trace impedances, signal velocity, buffer strengths, etc., within tolerances dictated by fabrication processing variations.

In static timing analysis (11), signal paths are ascertained by tracing the design connections and summing the worst (or best) case delays. This approach can account for delay relations between clock and data signals, and detect several types of timing violations including setup and hold, period and duty cycle, race conditions and skew checks. However, static timing analysis differs from functional debug and does not consider functional behavior of the circuit.

FIGURE 8 illustrates that for common clock scheme, skew can influence both setup (Ts) and hold (Th) margins but jitter affects only the setup. The CLK@Receiver and CLK@Driver are clock signals probed at data driver and receiver pins. The clock edges (the upper left side) utilized for skew (Tskw) measurements are regarded as reference. The DQ@Driver and DQ@Receiver are data signals at driver and receiver ICs.

[FIGURE 8 OMITTED]

As further example of jitter and skew effects, consider a common clock bus operating at 133 MHz (minimum clock period = 7.5 ns).

Allow maximum skew of 225 ps and edge-to-edge jitter 175 ps.

The minimum effective period (= minimum period - maximum jitter - maximum skew) is

(7.5 ns - 0.175 ns - 0.225 ns) = 7.1 ns.

Subsequently, the maximum allowed delay for inner chip (silicon) and interconnect is 7.1 ns.

Based on timing relations between a data and clock signals, one way to enhance setup margin is to shorten the data trace (or lengthen clock trace) at the price of lowering the hold margin. Conversely, hold margin can be improved by lengthening the data line or shortening the clock line (but at the expense of the setup margin). An alternative way to increase setup margin is by increasing the clock period (lowering operation frequency); this will not affect the hold margin (12), which is independent of clock frequency.

Common clock timing techniques have certain limitations. The minimum cycle time (which defines the highest frequency) is limited by the maximum delays. Consequently, there is a dependence on absolute delays. The common clock timing techniques are limit ed to medium speed (i.e., frequencies below ~ 200 to 300 MHz) buses. (6)

Therefore, an alternative approach such as source synchronous signaling is required to achieve higher operational frequencies.

ACKNOWLEDGEMENTS

Thanks to Peter Arnold, Clement Yuen, Richard Kuo and Dean Gonzales for valuable comments.

REFERENCES

(6.) Stephen H. Hall, Garrett W. Hall, James A. McCall, "High-Speed Digital Systems Design, A Handbook of Interconnect Theory and Design Practices," John Wiley and Sons Inc. 2000, PP. 178-193.

(7.) Eric Bogatin, "Signal Integrity--Simplified," Prentice Hall, 2004, P. 3

(8.) "PCI-X Addendum to the PCI Local Bus Specification" Revision 1.0, June 17, 1999, PP. 186-187.

(9.) Lynne Green, "Timing Correction for Flight Time Compensation," Application Note

(10.) "IBIS (I/O Buffer Information Specification)" Version 4.1, January 30, 2004, P. 12, PP. 26-28, P. 48.

(11.) Bruno A. Messina, "Timing Your PCB Design," Printed Circuit Design, May 1998, PP. 31-34.

(12.) Bob Kirstein, "Practical timing analysis for 100-MHz digital designs" EDN, August 2002, PP. 95-104.

ABE (ABBAS) RIAZI is a senior staff electronic design scientist with Server-Works (a Broadcom company) in Santa Clara, CA. He can be reached at a [e-mail]

TABLE 1. Timing formulas and parameters for a common-clock bus.

EQUATION 1

Tsu_mrg = [Tcyc - Tco_dq,max-(Tpcb_skw,max+ Tclk_skw, max+ Tjtr) - T
  su,min - Tflt_dq,max]

EQUATION 2

Thld mrg = [Tco_dq,min + (Tclk_skw, max + Tpcb_skw, max)- Thld,min +
  Tflt_dq,min]

With timing parameters as defined below:

Tsu_mrg = Steup timing margin.       Thld_mrg = Hold timing margin.
Tcyc = Clock cycle time (period).    Tjtr = Time variation in adjacent
                                       clock periods (jitter).

Tclk_skw, max= Output clock buffer skew (maximum).
Tpcb_skw, max= PCB flight time skew for clock traces (maximum).

Tco_dq,max = Driver's data output valid delay (maximum).
Tco_dq,min = Driver's data output valid delay (minimum).

Tsu,min = Receiver's input setup requirement (minimum).
Thld,min = Receiver's input hold requirement (minimum).

Tflt_dq,max = Signal flight time (maximum).
Tflt_dq, min = Signal flight time (minimum).