Tiempo Chooses Verific Design Automation's SystemVerilog Front End.SystemVerilog Analyzer, Static Elaborator Serve as Front End to New Synthesis Software for Asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end. Chip Design ALAMEDA, Calif. -- Tiempo, provider of breakthrough, ultra low-power asynchronous intellectual property (IP) for embedded applications, has chosen Verific Design Automation, a de facto [Latin, In fact.] In fact, in deed, actually. This phrase is used to characterize an officer, a government, a past action, or a state of affairs that must be accepted for all practical purposes, but is illegal or illegitimate. industry standard, as the front end for its software products. Tiempo licenses Verific's SystemVerilog analyzer and static elaborator to serve as the front end to its Asynchronous Circuit Compiler (ACC See adaptive cruise control. ), synthesis software that generates asynchronous and delay-insensitive circuits from a model written in SystemVerilog. "Verific's software serves as an essential component of our product development plan and gave us an immediate head start on worldwide product deployment," remarks Serge Maginot, chief executive officer of Tiempo. Verific's software serves as the front end to Field Programmable Gate Array See FPGA. (FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. ) and Electronic Design Automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tools, such as Tiempo's ACC, for exploring, navigating, analyzing, modifying and documenting designs. All are written in platform-independent C++ that compiles on Solaris, HP-UX HP's version of Unix that runs on its 9000 family. It is based on SVID and incorporates features from BSD Unix along with several HP innovations. (operating system) HP-UX - The version of Unix running on Hewlett-Packard workstations. , Linux and Windows platforms. Each is licensed as source code and come with support and maintenance. Michiel Ligthart, Verific's chief operating officer Chief Operating Officer (COO) The officer of a firm responsible for day-to-day management, usually the president or an executive vice-president. , notes: "Tiempo's innovative product strategy and roadmap make it clear that this is a company to watch. I was excited to learn how its team applied our SystemVerilog parser to the problem of asynchronous synthesis. Verific is pleased to have a role in its success." About Tiempo Tiempo develops and markets innovative Core IPs for the design of chips that are ultra-low power/noise/voltage, robust versus PVT variations and secured. Tiempo IP portfolio includes asynchronous and delay-insensitive cores of microcontrollers, microprocessors and crypto-processors, and is supported by an automated synthesis tool that uses SystemVerilog as input language. Targeted core applications are chips for low-power embedded electronics and secured devices. Tiempo is located at: 110 rue Blaise Pascal, 38330 Montbonnot, France. Telephone: +33 4 76 61 10 00. Facsimile number: +33 4 76 44 19 69. Email: sales@tiempo-ic.com. Website: www.tiempo-ic.com. About Verific Design Automation Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific's software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: www.verific.com. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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