The latest in underfill for advanced chip assembly: is a low-cost, surface-mount-compatible process possible?In component-level assembly, underfill materials are commonly used to reduce the thermal stresses on the solder solder (sŏd`ər), metal alloy used in the molten state as a metallic binder. The type of solder to be used is determined by the metals to be united. Soft solders are commonly composed of lead and tin and have low melting points. Hard solders (i. joints due to the mismatch mismatch 1. in blood transfusions and transplantation immunology, an incompatibility between potential donor and recipient. 2. one or more nucleotides in one of the double strands in a nucleic acid molecule without complementary nucleotides in the same position on the other of coefficient of thermal expansion coefficient of thermal expansion, n See expansion, thermal coefficient. (CTE (Coefficient of Thermal Expansion) The difference between the way two materials expand when heat is applied. This is very critical when chips are mounted to printed circuit boards, because the silicon chip expands at a different rate than the plastic board. ) between the silicon chip and the organic substrate. The underfill improves the reliability of flip chip A chip packaging technique in which the active area of the chip is "flipped over" facing downward. Instead of facing up and bonded to the package leads with wires from the outside edges of the chip, any surface area of the flip chip can be used for interconnection, which is typically done , chip-scale packaging (CSP (1) (Certified Systems Professional) An earlier award for successful completion of an ICCP examination in systems development. See ICCP. (2) (Commerce Service P ) and ball grid array “BGA” redirects here. For other uses, see BGA (disambiguation). A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. (BGA (Ball Grid Array) A popular surface mount chip package that uses a grid of solder balls as its connectors. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used. ) assembly systems. Two types of underfill materials are used in current electronics packaging manufacturing: conventional capillary capillary (kăp`əlĕr'ē), microscopic blood vessel, smallest unit of the circulatory system. Capillaries form a network of tiny tubes throughout the body, connecting arterioles (smallest arteries) and venules (smallest veins). flow materials and fluxing no-flow materials. Conventional underfill materials are implemented by capillary flow process. The capillary flow of underfill material with free filler particles takes a very long time to fill the gap between the silicon chip and the organic substrate. (1) The full cure of capillary underfill material also takes tremendous time, up to hours. Some innovative underfill methods have been developed to deal with these issues. (2,3) Among them, fluxing no-flow underfill is the most promising one with its reduced processing time and no post cure. (4) This process dispenses the desired volume of fluxing underfill material on the chip locations prior to the component placement. The underfill cure is accomplished concurrently with solder joint formation in the reflow (1) The process of heating and melting the solder that has been screen printed onto a printed circuit board in order to bond chips and other components to the board. Surface mount chips (SMT) use the reflow method. Contrast with wave soldering. See also reflowable text. process. Although the fluxing no-flow underfill process is much faster than the conventional capillary flow process, it has three intrinsic manufacturing and material-related disadvantages. The first disadvantage is processing time. In the fluxing underfill process, the process step of underfill material dispensing is inevitable. The prevailing method of implementing fluxing underfill material in flip chip assembly is by needle dispensing material on the printed circuit board (PCB PCB: see polychlorinated biphenyl. PCB in full polychlorinated biphenyl Any of a class of highly stable organic compounds prepared by the reaction of chlorine with biphenyl, a two-ring compound. ). The dispensing process is a point-by-point or line-by-line discrete operation. The second disadvantage is the increased manufacturing cost. To optimize the production cycle time of an assembly production line, one or two underfill dispensing machines are required for a production line. The capital cost of one of these machines can range from US$100,000 to US$500,000. The maintenance and overhead costs overhead costs see fixed costs. for underfill dispensing machines are also substantial. The third disadvantage of fluxing underfill is related to the material properties of fluxing no-flow underfill. The fluxing underfill materials have no filler content because of the concern about solder joint yield. Consequently, the CTE of this material is higher than that of conventional capillary flow underfill materials. In this research, a process and associated module have been developed to resolve the first two manufacturing concerns with the fluxing no-flow underfill process--the long processing time and high manufacturing cost associated with underfill dispensing. This novel process is high-speed surface-mount compatible without involving the underfill dispensing operation and dispensing equipment. It eliminates the discrete underfill dispensing process step in flip chip, CSP and BGA assembly. Dispenseless Underfill Process The prevailing process of implementing underfill materials is shown in Figure 1. The material is held in a syringe syringe /sy·ringe/ (si-rinj´) (sir´inj) an instrument for injecting liquids into or withdrawing them from any vessel or cavity. with a needle on one end and pressured air at the other end. The dispensing machine deposits the desired volume of material at the chip location on the PCB prior to the reflow process. The placement force pushes the chip down and compresses the material underneath the chip. [FIGURE 1 OMITTED] The developed dispenseless process integrates the underfill application and chip placement into one process step. It enables shorter processing time and lower manufacturing cost by eliminating usage of the underfill dispensing machine. This underfill process is shown in Figure 2. [FIGURE 2 OMITTED] Besides the benefit of cost savings from the capital and overhead costs of underfill dispensing machines, this process also provides a solution for the long processing time encountered by the current underfill dispensing process. Since the underfill application is integrated into the placement process, the processing time of discrete underfill dispensing is eliminated. The processing time for this innovative process (underfill application plus placement) is almost as fast as the sole placement process. The two manufacturing issues associated with current dispensing underfill process (long processing time and high manufacturing cost) are resolved by this dispenseless process. Dispenseless Module Design and Development A dispenseless underfill module has been developed and integrated into a commercial chip placement machine (Figure 3). Such a dispenseless underfill module ensures the full compatibility with the mainstream placement machines in the current electronics assembly manufacturing industry. The process parameters (placement force, part vision setting, etc) have been investigated to construct an optimized process. [FIGURE 3 OMITTED] Prototyping Validation Flip chips on organic board test vehicles have been successfully assembled utilizing this dispenseless fluxing underfill module and process. The flip chips are FA 10-4X4 die. The die size is 10.1 mm by 10.1 mm. A commercial available fluxing no-flow underfill material is used in the prototyping. The pre-reflow and post-reflow flip chip on organic board assembly is shown in Figure 4 and Figure 5, respectively. [FIGURES 4-5 OMITTED] Results and Discussion Based on the flip chip on board prototyping utilizing this dispenseless underfill process, the characteristics of this process are discussed in the following sections. Processing Time The flip chip test vehicles assembled by this innovative process show that the processing time of the whole chip placement and underfill application process is less than 3 seconds, excluding the board-in and board-out transportation time. The current dispensing underfill process takes about 16 seconds to finish the same process: about 3 seconds to dispense underfill material at one chip location, about 10 seconds for board transfer time from the underfill dispensing machine to the chip placement machine, and 3 seconds for chip placement. For a board with high chip counts (such as 50 chips per board), the dispenseless underfill process shortens the processing time dramatically. Manufacturing Cost The dispenseless underfill process eliminates the underfill dispensing machines in the electronics assembly production line. The direct saving from the capital cost of one underfill dispensing machine ranges from US$100,000 to US$500,000. The maintenance and overhead cost savings due to the streamlined production are also substantial. Besides these benefits, the production line cycle-time balance issue caused by the long processing time in underfill dispensing is resolved when utilizing the dispenseless underfill process. The production line achieves the highest productivity with the lowest cycle time due to the integration of underfill application and chip placement. Interconnect Yield The electrical continuity of the flip chip test vehicles was tested after the reflow process. The daisy chains Connected in series, one after the other. Transmitted signals go to the first device, then to the second and so on. A SCSI Daisy Chain Both internal and external SCSI devices are daisy chained together. inside the FA 10-4x4 flip chip assembly were measured using a sourcemeter. The electrical test showed that solid solder interconnects are formed between the silicon chip and the organic substrate. The pre-reflow x-ray inspection shows the chip placement accuracy is well maintained (Figure 4). The underfill application at placement process does not introduce a misalignment mis·a·ligned adj. Incorrectly aligned. mis a·lign ment n. issue
with the chip placement.
Interface Integrity The quality of the chip-underfill interface and the board-underfill interface were investigated by scanning acoustic microscopy microscopy /mi·cros·co·py/ (mi-kros´kah-pe) examination under or observation by means of the microscope. mi·cros·co·py n. 1. The study of microscopes. 2. (CSAM CSAM Credit Suisse Asset Management CSAM College of Science and Mathematics CSAM California Society of Addiction Medicine (San Francisco, California) CSAM Certified Senior Account Manager ). The CSAM images show that the integrity of interfaces inside the flip chip assembly are within specification (Figure 6). No delamination delamination /de·lam·i·na·tion/ (de-lam?i-na´shun) separation into layers, as of the blastoderm. de·lam·i·na·tion n. 1. A splitting or separation into layers. 2. is found on the chip-underfill interface or the board-underfill interface. The underfill void spots areas are much less than those using the standard dispensing underfill process. [FIGURE 6 OMITTED] Reliability The underfill fillet fillet /fil·let/ (fil´et) 1. a loop, as of cord or tape, for making traction on the fetus. 2. in the nervous system, a long band of nerve fibers. fil·let n. 1. shape and voids prove to be two critical factors that impact the reliability of flip chip on board assembly. Insufficient underfill material at the fillet region reduces the reliability of the flip chip assembly. Uniform underfill fillet at chip edges and chip corners helps to improve the reliability of flip chip assembly. The dispenseless underfill process ensures the uniformity of underfill volume on the entire chip bottom side, particularly sufficient underfill volume near the edges of a chip (Figure 7). The flip chip assembly utilizing the dispenseless underfill process shows a better fillet shape comparison to that of dispensing underfill process. For the same underfill material, the void quantity and volume in a flip chip assembly by dispensing underfill process is higher than that assembled by dispenseless underfill process. The flip chip on board assembled by dispenseless underfill process has higher reliability. [FIGURE 7 OMITTED] Conclusions A dispenseless underfill process and associated module have been developed in this research. The novel process streamlines the electronics assembly production line and saves substantial capital, maintenance and overhead cost by eliminating the use of an underfill dispensing machine. This process also shortens the manufacturing time. Flip chip assemblies have been successfully assembled by utilizing this innovative process. The flip chip test vehicles assembled by this process show that chip placement accuracy, interconnects yield and integrity of interfaces inside the flip chip assembly are within specifications. The flip chip assembly forms better underfill fillet at the flip chip edges, has less voids in the underfill and has higher reliability than that assembled by the dispensing underfill process. This process also possesses the intrinsic self-adjustment ability to automatically meet the underfill volume requirements for different chips. This invention has industrial applications and commercial value. It is fully compatible with the standard surface-mount infrastructure available in the industry. The dispenseless underfill module can be implemented on top of the existing electronics assembly production equipment with an adding-on module. All commercial available no-flow underfill or fluxing underfill materials can be used in this process. It demonstrates that the process invention is an active and revolutionary driver in the microelectronic packaging and assembly industry. The philosophy of process-oriented equipment design ensures the overall cost-effectiveness ha electronics manufacturing This article presents a typical manufacturing process of an electronic assembly. Component manufacturing Components such as resistors, capacitors and integrated circuits are generally made by specialized contractors. . Acknowledgments The authors would like to thank the Center of Advanced Board Assembly at Georgia Institute of Technology Georgia Institute of Technology, in Atlanta, Ga.; coeducational; state supported; chartered 1885, opened 1888. It is a member school in the university system of Georgia. Significant among its facilities and programs are the Frank H. , Engent (formerly Siemens Dematic Advanced Electronic Assembly Technology Center) and Phoenix International for support of this research. References (1.) S. Han, K.K. Wang, "Analysis of the flow of Encapsulant en·cap·su·lant n. A material used for encapsulating. During Underfill Encapsulation (1) In object technology, the creation of self-contained modules that contain both the data and the processing. See object-oriented programming. (2) The transmission of one network protocol within another. of Flip Chips," IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. trans. On Component, Packaging, and Manufacturing Technology, Part B, Vol. 20(4), 1997, pp.424-433. (2.) K. Gilleo, B. Cotterman, and T. Chen, "Molded Underfill for Flip Chip in Package," HDI HDI Human Development Index (UNDP yardstick of human welfare) HDI Help Desk Institute HDI Humpty Dumpty Institute (New York, New York) HDI High Density Interconnect , June, 2000, pp.28-30. (3.) H.H. Shi, M. Mizutani, H. Noro, M. Kuwamura, A. Kuroyanagi, H. Ito, T. Harada, and S. Tto, "Spacial spa·cial adj. Variant of spatial. Adj. 1. spacial - pertaining to or involving or having the nature of space; "the first dimension to concentrate on is the spatial one"; "spatial ability"; "spatial awareness"; "the spatial Characteristic of Future Flip Chip Underfill Materials and the Process," Proceedings of the 50th ECTC ECTC Electronic Components and Technology Conference ECTC Erosion Control Technology Council ECTC Earth Commission for Thermostatic Control (from environmentalist book The Weather Makers) ECTC Expected Cost to Company , 2000, pp.1661-1665. (4.) C.P. Wong, S.H. Shi and G. Jefferson, "High Performance No-Flow Underfill for Low-Cost Flip Chip Applications: Material Characterization," IEEE trans. On Component, Packaging, and Manufacturing Technology, Part A, Vol. 21(3), 1998, pp.450-458. James Jian Zhang is a Ph.D. candidate; email: gte665q@prism.gatech.edu; and Dr. Daniel F. Baldwin is Baldwin I, Latin emperor of Constantinople Baldwin I (bôl`dwĭn), 1171–1205, 1st Latin emperor of Constantinople (1204–5). The count of Flanders (as Baldwin IX), he was a leader in the Fourth Crusade (see Crusades). an associate professor; email: daniel.baldwin@me.gatech.edu--both with the George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA. |
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