The future of boundary scan: combining JTAG with methods such as flying probe can improve test coverage and speed.

Today's production environments and manufacturing schedules force test engineers to provide flexible low-cost test solutions in the shortest possible time. These steps include design entry, prototype verification, production, final assembly and also test and debugging at various stages throughout this process. For example, concurrent design and development of circuitry, housings, and firmware and user software can shorten the product design cycle. Thinking in the early stages of product design about the test strategies to be applied in design, prototyping, manufacturing and in the field avoids costly delays as well as insufficient test access and test coverage throughout the product's life cycle. One of the most efficient test technologies for electronics is boundary scan (1) (IEEE 1149.1, aka JTA[G.sup.2]), targeting many of the problems today's test engineers are facing.

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Boundary scan as board-level technology is well established. In recent years many chip designers started to use the Test Access Port (TAP), defined in IEEE Std. 1149.1, to access self-test circuitry built into the IC. This permits designers and test engineers to run the IC's built-in self test[s.sup.3] at the board and system levels. Such tests verify IC functionality, often at functional speed, and the connectivity at chip level. Furthermore, new BIST algorithms developed by various companies also permit test of board and system level interconnections between ICs at functional speed (standard boundary scan using the EXTEST instruction can be considered a quasi-static test).

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In addition to connectivity tests, boundary scan is also used to program devices such as serial EEPROM and flash EEPROM mounted on the printed circuit board (on-board or in-circuit programming--ICP).

Heiko Ehrenberg is CEO of Goepel Electronics LLC (goepel.com); [e-mail].