The basics of boundary scan: this technique permits reuse of test data and cuts costs by eliminating ICT and functional test.

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Even though most test engineers feel feel knowledgeable with the current test technologies, surveys show that there still is a lack of understanding of JTAG (boundary scan). What exactly is boundary scan? Where can it be used? How does boundary scan work? And, most important: What advantages does it have over other test procedures?

Boundary scan is possibly the most resourceful test technique which, similar to in-circuit test (ICT) but without physical contact, detects failure location, sets thousands of test points--including under BGAs--and needs only four lines (Figure 1).

[FIGURE 1 OMITTED]

After lengthy discussions about the principles of testing through the stimulation and read-out of integrated thresholds in an IC in the 1980s, boundary scan became a standard (IEEE 1149.1) in 1991. Boundary scan means "testing at the periphery (boundary) of an IC." Besides the core logic and contact points, some additional logic is implemented in an IC. These test points are integrated between the core logic and the physical pins. All boundary scan cells are combined in a shift register with parallel inputs and outputs and generate the serial scan path.

In each boundary scan IC a control logic, the test access port (TAP), is integrated to stimulate and read-out the cells. The IC is controlled by four signals. Asynchronous actions inside the TAP are executed at the edges of the test clock (TCK) signal, and the TAP's single states are fixed at each increasing edge, depending on TMS (test mode select). TDI (test data in) and TDO (test data out) represent the input and output of the serial boundary scan shift register (Figure 2).

[FIGURE 2 OMITTED]

Stefan Meissner is with Goepel Electronic (goepel.com); [e-mail].