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The Saga of the Heavy-Handed No-Clean Flux -- An investigation into the interactions of water-based flux andalternative board finishes.


Recently, we conducted a research investigation into the process interactions of a water-based flux with an alternative board finish. A client asked us to assess a new process in which he used Dexter FST See flat screen.  immersion tin, fluxed with Kester 977 low solids, VOC (Vertical Online Community) See vertical portal.  free, no-clean wave solder flux. This investigation consisted of two phases: (1) to evaluate a process in which an extra heavy application of liquid fluxing was used and (2) to evaluate the same process, but with a typical application of liquid fluxing used. Both immersion tin groups used hot air solder leveling (HASL (language) HASL - SASL plus conditional unification.

["A Prological Definition of HASL, A Purely Functional Language with Unification Based Conditional Binding Expressions", H. Abramson in Logic Programming: Functions, Relations and Equations, D. DeGroot et al eds, P-H 1986].
) boards as controls.

The electrical effects of the residues were assessed using surface insulation resistance Surface insulation resistance is a property of the material and electrode system. It represents the electrical resistance between two electrical conductors separated by some dielectric material.  (SIR) test methodology per J-STD-001C, Appendix B (IPC-TM-650, method 2.6.3.3A) on the CSL Umpire test board. The CSL Umpire board is designed to evaluate the following patterns: 68 pin leadless chip carrier A chip package that uses flat metal pads that make contact with the socket or circuit board. Contrast with leaded chip carrier. See CLCC.  (LCC); 80 pin tiny quad flat pack (TQFP See QFP. ); 256 in and out (IO) ball grid array “BGA” redirects here. For other uses, see BGA (disambiguation).

A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits.
 (BGA); pin grid array See PGA.

(hardware) Pin Grid Array - (PGA) A style of integrated circuit socket or pin-out with pins laid out on a square or rectangular grid with a separation of 0.1 inch in each direction. The pins near the centre of the array are often missing.
 (PGA (1) (Professional Graphics Adapter) An early IBM PC display standard for 3D processing with 640x480x256 resolution. It was not widely used.

(2) (Programmable Gate Array) See gate array and FPGA.
) socket; 16 pin dual in-line package See DIP.

(hardware) Dual In-Line Package - (DIL, DIP) The most common type of package for small and medium scale integrated circuits, with up to about 48 pins. The pins hang vertically from the two long edges of the rectangular package, spaced at intervals of 0.1 inch.
 (DIP); and B24 comb patterns on the bottom side (16 SIR patterns in all). Additional analysis of the residues was accomplished using ion chromatography (IC) per IPC-TM-650, method 2.3.28.

Processing Conditions

For Phase 1, 10 immersion tin bare boards were no-clean pasted and reflowed. The boards were then fluxed with Kester 977 and soldered. The assemblies were placed in SIR chambers for 168 hours. An essential factor in Phase 1 processing was the amount of flux applied to each board-1500 microg/in2 by weight.

For Phase 2, 10 immersion tin boards were processed exactly as in Phase 1. The only difference was that the amount of Kester flux applied to each board was 750 microg/in2 by weight.

Phase I (Heavy Liquid Fluxing) Findings

The ten boards, with 12 SIR patterns per board, showed only the 68 pin LCC pattern failed the test criteria found in J-STD-001C, Appendix B. The cause of the failures was a low measured resistance pattern, most notably under the low standoff LCC devices, as well as metal migration on this LCC pattern. All other patterns, the BGA, TQFP, DIP, PGA, and B-24 passed the SIR testing. The failed area showed signs of excess flux trapped below the ceramic LCC. Three HASL processed boards also failed under the LCC.

All residues tested were well under our recommended maximums established for a no-clean assembly. Through IC, the process tested clean ionically for both immersion tin and HASL boards.

Phase II (Typical Liquid Fluxing) Findings

Since all other patterns passed the Phase I testing, SIR focus was only on the 68 pin LCC pattern of the 10 boards. Phase II findings show that all boards passed the test criteria found in J-STD-001C, Appendix B-including the three HASL boards.

All residues tested were well under our recommended maximums established for a no-clean assembly. Through IC, the process appeared clean.

What Does it All Mean?

We have long suspected that heavy fluxing could leave a pool of unreacted or partially reacted water-based flux under a component. Since water-based flux is a strong acid, its non-removal under a component could affect the electrical path of the circuit. Damage to the electrical path can cause electromigration or electrical leakage failures even if IC showed the assemblies were clean. In this study, we were able to create a dendrite dendrite: see nervous system; synapse.  that did not have a typical corrosive residue, but did leave a strong acid that caused electrical leakage under the LCC. Because of this study, the customer now has a protocol in place. A spray application of 750 microg/in2 per board of water-based flux, when applied evenly, will produce acceptable assemblies.

The Moral of the Saga

Flux applications near 1500 ug/in2 (heavy fluxing) of a water-based, no-clean flux, in areas entrapped under components, will leave a strong acid residue that can cause electromigration failures on immersion tin and HASL boards. The new process proves that Dexter FST immersion tin, fluxed with Kester 977 low solids, VOC free, no-clean wave solder flux works well when fully activated (heated).

---

Terry Munson and Pat Kane are with Contamination Studies Laboratory (CSL), Kokomo, IN; (765) 457-8095; e-mail: Residuguru @aol.com and CSL PAT@aol.com; Web page: www.residues .com.

http://www.circuitsassembly.com

Copyright [copyright] 2001 CMP CMP (cytidine monophosphate): see cytosine.


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Article Details
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Author:Kane, Pat
Publication:Circuits Assembly
Article Type:Brief Article
Geographic Code:1USA
Date:Apr 1, 2001
Words:719
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