Tharas Systems to Demonstrate Hardware Accelerator At Synopsys Users Group San Jose 2000 March 13-15.

Business Editors

SANTA CLARA, Calif.--(BUSINESS WIRE)--March 13, 2000

Prototype Version Accelerates Simulation Functions

Electronic Design Automation (EDA) supplier Tharas Systems Inc., based here, will demonstrate this week a working prototype of its next-generation hardware accelerator during the 10th Annual Synopsys User Group (SNUG) San Jose 2000 at the Doubletree Hotel.

Tharas Systems, named for the Sanskrit word that means rapid progress or velocity, is developing easy-to-use hardware accelerators for the register transfer level (RTL) of electronics design that fit within an existing verification environment. Its Hammer(R) 50/32 will improve a logic designer's ability to efficiently create and implement system-on-chip (SOC) designs by accelerating simulation and eliminating the verification bottleneck.

The initial version of Hammer to be demonstrated at SNUG accelerates several critical Verilog Hardware description Language (HDL)-based RTL simulation functions. Fully functional, production units of Hammer will be available before and demonstrated at the 37th Design Automation Conference to be held June 5-9 in Los Angeles.

"Initial customer feedback has been quite positive," says Steve Carlson, CEO of Tharas Systems, adding that the semiconductor industry has had a crying need for a solution to accelerate the verification phase of design. "All indications are that Hammer will meet designers' need to unblock the verification bottleneck."

Tharas Systems has solved a problem that previous generations of hardware accelerators did not -- that is, integrating the interconnect and communication between a large number of specialized processors. Previous attempts have used bus architectures that suffer from resource conflict and algorithmically intractable scheduling problems. By drawing on concepts from the networking industry, it developed an approach to hardware acceleration that uses application specific integrated circuits (ASICs) in a memory-mapped architecture, rather than a traditional field programmable gate array (FPGA) architecture.

The technology foundation is a combination of hardware and software. The software provides links to existing test and verification software, while the hardware delivers performance and capacity characteristics at a reasonable price.

Initial Functionality

Hammer was designed to work transparently within an existing RTL verification environment, offering fast compilation times.

In this initial release, Hammer's functionality accelerates Verilog RTL Code, including programming language interface (PLI) calls, as well as the interactive creation of function and system calls, commonly called VCD dumping, that are formatted as results data. Hammer operates within the existing simulation and debug environment by automatically creating co-simulation with the Synopsys VCS Verilog simulator.

The RTL code that Hammer accelerates includes arbitrary memory styles, unbounded numbers of clocks and asynchronous singals, arithmetic operation sections with datapath functionality and combinational blocks. The Hammer hardware provides extensive amounts of physical memory to allow mapping of RTL memories and to achieve high-performance memory access during simulation.

Arithmetic code segments are effectively executed by the specialized support of the Hammer architecture, which goes beyond smaller primitives with interconnect restrictions found in FPGA-based architectures. The architecture is scalable which translates to high-performance execution of combinatorial blocks.

PLI calls are ubiquitous in RTL-based designs, and not only used for debugging purposes. Instead, they are used for taking advantage of the standard Verilog system calls, or sometimes can be applied for user-defined functions, or even more complex C-based models for portions of the design. The Hammer architecture has been created to facilitate efficient execution of the PLI extensions to Verilog.

VCD dumping for signal tracing can add overhead to CPU time spent in a design simulation. The latest release of VCS (version 5.1) includes an option to analyze the amount of time spent in RTL, PLI and VCD dumping, compared to simulation kernel execution. For large designs, the time spent on signal tracing can be substantial. The Hammer hardware has a sophisticated interconnect matrix between execution elements, combined with hardware based signal trace buffers. This architecture relegates a major portion of signal tracing requirements onto the hardware, allowing for a faster execution of the global dumping process.

More details on the full product line will be unveiled by Tharas Systems in early 2000.

Pricing and Availability

Priced to be affordable for every designer, Hammer's list price will start at $200,000. For more specific product information, contact Steve Carlson at Tharas Systems. He can be can be reached at [phone] or via electronic mail at [e-mail].

About Tharas Systems

Tharas Systems is an EDA company focused on accelerating simulation and removing the verification bottleneck. Founded in 1998, it is privately held and funded by private investors from throughout the EDA and networking industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Telephone: [phone]. Facsimile: [phone]. Email: [e-mail]. On-line information is found at its Web Site: http://www.tharas.com.

Hammer is a registered trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.